Texas Instruments Corporation

T Damodar Reddy

Sung-Wei Lin

Tim M Coffman

Phat C Truong

Dennis R Robinson

A method for erasing blocks of a non-volatile memory includes detecting whether a block is in at least one of an erased state or a state secured from erasure; then setting a flag register at a first level for each block detected to be in at least one of an erased state or a state secured from erasure or at a second level for each block not so detected; then selecting for erasure blocks that have their respective flags set at the second level; and then erasing the selected blocks.

Smart erase algorithm with secure scheme for flash EPROMs

The power-on-reset test circuit of this invention includes two imbalanced latches to detect the occurrence of a transient power-on-reset signal. The occurrence of a transient power-on-reset signal is latched for later verification during circuit testing. Both latches are designed to default to a low voltage output (Vss) on initial power-up. One of the latches is set by the power-on-reset signal to a high-voltage output (Vcc) state. The other latch is set by a reference-potential input to a low-voltage output state. If the set latch has a high-voltage output and the other latch has a low-voltage output, then the power-on-reset circuitry is functioning properly.

Circuit for testing power-on-reset circuitry

An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging. The pulse converter circuit (12) receives the array source detect signal (ASDET) and generates an erase completion signal (ERCTR) and a pulldown control signal ERCTR.sub.-- to control final discharge of the array source signals (AS) and indicate that normal memory access may resume. The pulse converter circuit (12) also generates a pulldown signal (ERD.sub.--) that controls discharge of the array source signals (AS) by preventing current surges from appearing on the array source signals (AS) during discharge.

Method and device for detecting and controlling an array source signal

The CMOS high-voltage sensor circuit has a voltage reference including, for example, of four N-channel MOS transistors; one pass-gate P-channel transistor; one current-mirror P-channel MOS transistor; and a conventional high-voltage sensor including, for example, of two P-channel MOS transistors and one N-channel MOS transistor. The sensor circuit of this invention generates a high-voltage signal at the output if the input voltage is greater than both the reference voltage plus two P-channel threshold voltages and the supply voltage Vcc plus two P-channel threshold voltages. The power-up or power-down sequence may be in any order without adversely affecting the operation of the circuit of this invention.

High-voltage sensor for integrated circuits

The power-on reset circuit of this invention includes a current-sensing circuit, a pulse-stretching circuit, and a voltage-reference circuit. The voltage-reference circuit consists, for example, of one N-Channel and one P-Channel MOS transistor. The circuit of this invention uses a static voltage reference comprised of CMOS transistors to detect the power-up condition. The circuit of this invention improves detection of a transient power-supply voltage Vcc loss and detects that power-supply voltage transient on both rising and falling edges.

Current-sensing power-on reset circuit for integrated circuits

The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.

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Nalgonda, India

T Damodar Reddy