Synopsys, Inc.

Sébastien Roger Delerse

Arturo Salz

Ching-Ping Chou

Jean-Philippe Colrat

Arnold Mbotchak

Alexander Rabinovitch

Cedric Jean Alquier

Luc Francois Vidal

Luc François Vidal

A method of capturing signals during hardware verification of a circuit design utilizes at least one field-programmable gate array (FPGA) and includes selecting, at run time and using one or more pre-compiled macros, a group of signals to be captured during verification of the circuit design and storing values of the group of signals in at least first and second random access memories disposed in the at least one FPGA. The first and second random access memories may be addressable spaces of the same random access memory.

High speed, low hardware footprint waveform

A hardware verification system according to one embodiment includes, in part, a plurality of programmable devices. The plurality of programmable devices include a master scheduler, a plurality of schedulers and a plurality of programmable delay elements. A first one of the plurality of schedulers is configured to receive one or more delay values associated with one or more of the plurality of delay elements. Each of the plurality of programmable delay elements corresponds to a delay. The first scheduler is further configured to send a parameter corresponding to the one or more delay values to the master scheduler, and generate one or more signals corresponding to the one or more delay elements in response to a control signal the first scheduler receives from the master scheduler.

Method and apparatus for modeling delays in emulation

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Mountain View, CA, United States of America

Sébastien Roger Delerse