Stmicroelectronics S.a.

Other

Sébastien Rieubon

Michael Kraemer

Serge Ramet

Philippe Level

A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected.

Method for detecting the locking of a phase-locked loop and associated device

The invention concerns counting circuitry for providing a corrected count value based on the number of rising and falling edges of an input signal occurring during a reference time period, the counting circuitry comprising a counter () arranged to provide a first count value based on one of the number of said rising edges of said input signal occurring during said reference time period, and the number of said falling edges of said input signal occurring during said reference time period; characterized in that said counting circuitry further comprises adjustment circuitry (-) arranged to generate a corrected count value by determining the state of said input signal at the start time () and end time () of said reference time period, and adjusting said first count value if the state of said input signal at the start of said reference time period is different from the state of said input signal at the end of said reference time period.

Counter with correction circuitry

An electronic circuit includes at least one differential pair of transistors, a control transistor switch, a first current source and a second current source. The second current source is connected to a common emitter node of the pair of transistors in order to accelerate the discharge of parasitic capacitances during a switching operation.

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Saint Jean de Moirans, France

Sébastien Rieubon