Taiwan Semiconductor Manufacturing Comp. Ltd.

Tsinghua University

Mackay Memorial Hospital

Szu-Ying Chen

Dun-Nian Yaung

Jen-Cheng Liu

Min-Feng Kao

Tzu-Hsuan Hsu

Meng-Hsun Wan

Feng-Chi Hung

Tzu-Jui Wang

Pao-Tung Chen

Sen-Hong Syue

Huicheng Chang

Jeng-Shyan Lin

Yee-Chia Yeo

Shu-Ting Tsai

Hsiao-Hui Tseng

Wei-Cheng Hsu

Ping-Yin Liu

Lan-Lin Chao

Yi-Shin Chu

Cheng-Chieh Hsieh

Wen-De Wang

Jung-Kuo Tu

Kuo-Chin Huang

Bruce C S Chou

Ya-Wen Chiu

Chen-Jong Wang

Liang-Yin Chen

Volume Chien

Li-Ting Wang

U-Ting Chen

Cheng-Po Chau

Yi Che Chan

Chih Ping Liao

Yu-Hao Shih

Hsing-Lung Chen

YungHao Wang

Yeur-Luen Tu

Chun-Feng Nieh

Su-Hao Liu

Xiaomeng Chen

Xin-Hua Huang

Chih-Hui Huang

Yu-Chang Lin

Shih Pei Chou

Chien-Tai Chan

Calvin Yi-Ping Chao

Chun-Han Chen

Tien-Shun Chang

Cheng-Tao Lin

Chia-Shiung Tsai

Chi On Chui

Yung-Cheng Lu

Tri-Rung Yew

Chun-Chieh Chuang

Chia-Cheng Chen

Chia-Wei Liu

Chung-Chuan Tseng

Shih-Pei Chou

Che-Hao Chang

Lun-Kuang Tan

Heng-Wen Ting

Yi-Fan Chen

Wen-Kai Lin

Chao-Yang Yeh

Chien-Chong Hong

Jeng-Hua Wei

Po-Kang Ho

Chie-Pein Chen

Chia-Chiung Tsai

Jia-Cherng Horng

Yi-Rui Chen

Bruce Cs Chou

A method of forming a semiconductor device includes etching trenches in a substrate to form fin structures, depositing a liner layer to line the trenches, filling the trenches with an insulating layer, performing an ion implantation process to the insulating layer, after performing the ion implantation process, recessing the insulating layer to form shallow trench isolation (STI) regions adjacent the fin structures, and forming a gate crossing the fin structures.

Formation method of shallow trench isolation

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.

Semiconductor devices and methods of manufacture thereof

In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the fist insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

Semiconductor device and method of forming same

A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.

Gate spacer and formation method thereof

A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl)CH), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.

Reducing K values of dielectric films through anneal

Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.

Device and method for high pressure anneal

The present disclosure relates to a method of forming an integrated chip. The method includes forming a gate stack over a front surface of a substrate. A mask layer is formed over at least a portion of the gate stack and a portion of the front surface. A plurality of dopants are implanted into one or more regions of the substrate that are not covered by the mask layer to form one or more doped isolation features in the substrate. The one or more doped isolation features are formed to have a convex portion at least partially under the gate stack.

Image sensor device

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first fin structure with a first height and a first width formed over the substrate, a second fin structure with a second height and a second width formed over the substrate, and an insulating stack formed over lower portions of the first and second fin structures. The second height can be substantially equal to the first height and the second width can be greater than the first width. A top surface of the insulating stack can be below top surfaces of the first and second fin structures.

Variable size fin structures

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

Stacked semiconductor structure and method

A semiconductor device includes a fin structure that protrudes vertically out of a substrate, wherein the fin structure contains silicon germanium (SiGe). An epi-silicon layer is disposed on a sidewall of the fin structure. The epi-silicon layer contains nitrogen. One or more dielectric liner layers are disposed on the epi-silicon layer. A dielectric isolation structure is disposed over the one or more dielectric liner layers.

Nitride-containing STI liner for SiGe channel

A device includes a semiconductor substrate, a gate dielectric over the semiconductor substrate, and a gate electrode over the gate dielectric. The gate electrode has a first portion having a first thickness, and a second portion having a second thickness smaller than the first thickness. The device further includes a source/drain region on a side of the gate electrode with the source/drain region extending into the semiconductor substrate, and a device isolation region. The device isolation region has a part having a sidewall contacting a second sidewall of the source/drain region to form an interface. The interface is overlapped by a joining line of the firs portion and the second portion of the gate electrode.

Gate electrodes with notches and methods for forming the same

A chip includes a semiconductor substrate, integrated circuits with at least portions in the semiconductor substrate, and a surface dielectric layer over the integrated circuits. A plurality of metal pads is distributed substantially uniformly throughout substantially an entirety of a surface of the chip. The plurality of metal pads has top surfaces level with a top surface of the surface dielectric layer. The plurality of metal pads includes active metal pads and dummy metal pads. The active metal pads are electrically coupled to the integrated circuits. The dummy metal pads are electrically decoupled from the integrated circuits.

Hybrid bonding with uniform pattern density

In an embodiment, a method includes forming a plurality of fins adjacent to a substrate, the plurality of fins comprising a first fin, a second fin, and a third fin; forming a first insulation material adjacent to the plurality of fins; reducing a thickness of the first insulation material; after reducing the thickness of the first insulation material, forming a second insulation material adjacent to the first insulation material and the plurality of fins; and recessing the first insulation material and the second insulation material to form a first shallow trench isolation (STI) region.

Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

Methods and apparatus for via last through-vias

A device includes a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a dielectric fin over the substrate, a first isolation region between the first semiconductor fin and the dielectric fin, and a second isolation region between the first semiconductor fin and the second semiconductor fin. The first semiconductor fin is disposed between the second semiconductor fin and the dielectric fin. The first isolation region has a first concentration of an impurity. The second isolation region has a second concentration of the impurity. The second concentration is less than the first concentration. A top surface of the second isolation region is disposed closer to the substrate than a top surface of the first isolation region.

Semiconductor structure and method of forming the same

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Toufen, Taiwan

Szu-Ying Chen