Cadence Design Systems, Inc.

Incentia Design Systems, Inc.

Cadance Design Systems, Inc.

Szu-Tsung Cheng

Patrick Charles McGeer

Patrick Scaglia

Alexander Saldanha

Michael Jude Meyer

Ihao Chen

Xuequn Xiang

A system and method are provided for selectively inferring latch elements in a circuit design from an event-driven hardware description language (HDL) file to an event-independent format. The method includes modeling the file as a plurality of data flow equations, analyzing the plurality of equations for uninitialized variables, and placing a latch at any utilized, uninitialized variable. Control signal information for an inferred latch is also derived during the data flow analysis.

Latch inference using dataflow analysis

A hardware design language V&plus;&plus; is described. V&plus;&plus; provides an automatically designed and implemented communications protocol, embedded by a compiler in the design itself. This protocol permits transparent, automatic communication between modules in a hardware design. The protocol generalizes current design practice and impacts neither the cycle time, nor the area, of a typical system. Incorporating this protocol in the language itself frees the designer from the task of writing communications code, and ensures that two communicating modules follow the same low-level protocol. In V&plus;&plus; each program is directly interpreted as a network of communicating finite state machines. The composition of two V&plus;&plus; programs is a V&plus;&plus; program, with well-defined, deterministic semantics.

Hardware design language for the design of integrated circuits

A method using at least a portion of a control data flow graph (CDFG) which includes multiple control structures in a computer readable storage medium representing at least a portion of a high level design language (HDL) description of an actual or planned logic circuit to evaluate a need for a sequential state element in the portion of the logic circuit comprising producing a graph structure in the storage medium by providing a path origination node in the storage medium; providing a path destination node in the storage medium; producing respective complete paths between the path origination node and the path destination node by separately concatenating each branch of a first control structure of the CDFG with each branch of a second control structure of the CDFG such that a different respective complete path is produced for each possible combination of a respective branch from the first control structure and a respective branch from the second control structure; associating respective complete paths with a respective control statements associated in the CDFG with corresponding branches that have been concatenated with other corresponding branches to produce such respective complete paths; and traversing respective complete paths of the graph information structure to determine whether there is a respective path that is not associated with a respective control statement.

Synthesizing sequential devices from hardware description languages (HDLS)

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Campbell, CA, United States of America

Szu-Tsung Cheng