Realtek Semiconductor Inc.

Szu-Ping Chen

Jui-Yuan Tsai

Yu-Pin Chou

Ching-Tzong Wang

Jin-Sheng Gong

Wen-Hsia Kung

Chi-Feng Wang

Cheng-Jui Chen

Yu Jen Lin

Kuo-Yang Li

An apparatus for mode detection for a display device includes a front-end circuit, adapted to fetch an image signal according to a determined mode to generate a fetched image signal, and to adjust the determined mode according to a control signal, and a back-end circuit, connected to the front-end circuit, adapted to process the fetched image signal according to the determined mode. The back-end circuit is adapted to generate an indication signal according to an abnormal status, wherein the back-end circuit comprises a buffer adapted to temporarily store the fetched image signal, and wherein the abnormal status comprises an underflow or overflow state of the buffer. The back-end circuit further includes a determining unit, connected to the front-end circuit and the back-end circuit, adapted to generate the control signal according to the indication signal indicating the determined mode needs to adjust.

Apparatus and method thereof

The invention discloses a mode detection circuit and a method thereof, for detecting an image signal, the image signal includes a horizontal resolution and the vertical resolution. The mode detection circuit includes a measuring unit, a calculation unit, and a decision unit. The measuring unit receives a clock signal and is used to count the clock signal to output a first counting value and the second counting value. The calculation unit is used to perform the calculation with the first counting value and the second counting value and thereby outputting a calculating value, wherein the calculating value outputted by the calculation unit is corresponding to the ratio of the first counting value to the second counting value. The decision unit is used to determine the horizontal resolution or the vertical resolution according to the calculating value.

Mode detecting circuit and method thereof

A DC level redistribution method includes the steps of: receiving all positive signals and one negative signal of a plurality of pairs of differential signals; fixing a DC level of a positive signal of a designated pair of differential signals among a plurality of pairs of differential signals as a reference in order to adjust a DC level of a negative signal of the designated pair of differential signals for generating an adjusted negative signal; and taking the adjusted negative signal of the designated pair of differential signals as a reference in order to adjust DC levels of the positive signals of the other pairs of differential signals excluding the designated pair of differential signals. The DC redistribution method may be used in a display system.

Method and apparatus for DC level redistribution

The present invention relates to a circuit for updating firmware of a display apparatus and a method thereof. An optional update unit may be used for initializing the updating process. The first firmware information of the first display apparatus is transmitted to the second display apparatus for updating the second firmware information of the second display apparatus. Hence, reliability is enhanced and problems of incompatibility will not occur. In addition, no extra burning devices will be necessary, thus reducing extra cost.

Circuit for updating firmware of display apparatus and method thereof

A sync signal acquisition device is disclosed which comprises a transistor, a resistor, a clamper, an analog multiplexer and a comparator. While operating in a composite HS mode, prior to the generation of the sync signal HS, the invention uses a conventional circuit to extract a composite sync signal at start-up, thereby allowing related circuits to generate the sync signal HS and a clamping signal. Then, a mode selecting signal is used to disable the automatic clamping mode and switch the analog multiplexer to a forced clamping mode. At this point, the output voltage of the damper is set by a user instead of process; accordingly, the DC voltage level is more controllable, but not subject to drift due to process changes or temperature changes.

Sync signal acquisition device

An analog front end device with temperature compensation is provided. The analog front end device comprises a bandgap voltage reference circuit, a clock generator, a temperature compensation circuit, one to three identical converting circuits and a Sync-on-Green circuit. The temperature compensation circuit is adapted to sense the temperature variations of the analog front end device and dynamically compensate the bandgap voltage reference circuit, the clock generator and the Sync-on-Green circuit as the temperature varies, which thereby controls the thermal drift in the analog front end device.

Analog front end device with temperature compensation

A method for digitally filtering a video signal comprises: converting the video signal into a plurality of sampled values; determining whether distribution of at least one portion of the sampled values belongs to one of a plurality of specific types according to the sampled values; and generating a plurality of output values according to a correction operation corresponding to the one of the specific types.

Apparatus for digitally filtering a video signal, and related method

A synchronization control apparatus for driving a display module in an interlacing scan mode includes: a delay circuit for delaying an input vertical sync (IVS) signal to generate a delayed signal; and a multiplexer coupled to the delay circuit for selecting one of the IVS signal and the delayed signal according to an odd/even field indication signal to generate an output vertical sync (OVS) signal.

Synchronization control apparatus and method

An image signal processing method adapted to an AFE device, which respectively generates first and second colors of digital signals according to first and second colors of analog signals. First, the first color of odd and even signals and the second color of odd and even signals are generated according to the first and second colors of analog signals, respectively. In a single channel mode, the first color of odd or even signal serves as the first color of digital signal for output, and the second color of odd or even signal serves as the second color of digital signal for output. In a dual channel mode, the first color of odd signal and second color of even signal are synchronously outputted, and the first color of even signal and second color of odd signal are also synchronously outputted. The first color of odd and even signals are combined to form the first color of digital signal, and the second color of odd and even signals are combined to form the second color of digital signal.

Growing community of inventors

Chupei, Taiwan

Szu-Ping Chen