Orise Technology Co., Ltd.

Szu-Mien Wang

Dan-Chi Yang

Shih Chuan Huang

The present invention relates to an integrated circuit (IC) for SRAM (Static Random Access Memory) standby power reduction in LCD (Liquid Crystal Display) driver. The IC layout mainly disposes a high-current endurable transistor between a power supply pad and a power supply metal layer of the SRAM matrix. When the IC enters a standby mode, the electrical interconnection between the power supply pad and the power supply metal layer of the SRAM is cut off through the transistor so that the leakage current and the power consumption of the SRAM can be reduced.

Integrated circuit for SRAM standby power reduction in LCD driver

The present invention relates to a method for frame memory access and a display driver using the same. The method is a data moving method for allowing a display driver integrated circuit built in a portrait style frame memory to be used in a landscape mode. The spirit of the method is to repeatedly read data from the portrait style frame memory to the shift register, and move the data on the shift register to put the data to the correct data latch to constitute complete scan line data. Therefore, the portrait style display driver integrated circuit may drive a landscape mode display panel.

Method for frame memory access and display driver using the same

An SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities includes a memory cell array comprised of a plurality of single-port memory cells with dual-port capability, a first and a second port access units connected to the memory cell array in order to access the memory cells, and an access arbiter connected to the first and the second port access units in order to arbitrate a first port access request, a second port access request and a hidden refresh request.

SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities

The present invention relates to a memory repair circuit and a repairable pseudo-dual port static random access memory (pseudo-dual port SRAM). The memory repair circuit uses fewer redundant column blocks and stores a few failed block addresses to reduce the required complexity of decoding the redundant column blocks. Thus, the present invention can reduce a layout area required by redundant memory cells.

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Taipei, Taiwan

Szu-Mien Wang