Taiwan Semiconductor Manufacturing Comp. Ltd.

Szu-Hung Yang

Po-Zen Chen

Chih-Cherng Jeng

Chun-Yuan Hsu

Che-Min Lin

Chao-Lung Chen

Hung-San Lu

Hung-Chang Chang

Chao Yuan Chang

Ping-Ching Jiang

Chun-An Kung

Chin-Hsin Hsiao

Wen-Chun Hou

Kuo-Cheng Lee

Sheng-Liang Pan

Keng-Ying Liao

Chih-Kang Chao

Chia-Ching Tsai

Sen-Fu Chen

Chia-Yang Hung

Zhe-Ju Liu

I-i Cheng

Ching-Wen Cho

Kuo-Su Huang

Yu-Chih Chen

Jen-Shiang Leu

Kuang-Peng Lin

Weng-Liang Fang

Chiung Wen Hsu

Chai-Der Chang

Hung-Lung Hu

Chi-Chin Hsu

Jow-Feng Lee

Kuwi-Jen Chang

Jyh-Ping Wang

Shing-Jzy Tay

A plating apparatus for electroplating a wafer includes a housing defining a plating chamber for housing a plating solution. A voltage source of the apparatus has a first terminal having a first polarity and a second terminal having a second polarity different than the first polarity. The first terminal is electrically coupled to the wafer. An anode is within the plating chamber, and the second terminal is electrically coupled to the anode. A membrane support is within the plating chamber and over the anode. The membrane support defines apertures, wherein in a first zone of the membrane support a first aperture-area to surface-area ratio is a first ratio, and in a second zone of the membrane support a second aperture-area to surface-area ratio is a second ratio, different than the first ratio.

Plating apparatus and method for electroplating wafer

A semiconductor device includes a semiconductor substrate, a device layer over the semiconductor substrate, a first color filter in a top surface of the device layer and adjacent to an edge of the device layer, and a second color filter in the top surface of the device layer. The second color filter has substantially the same thickness and the same color as the first color filter.

CMOS image sensor structure with crosstalk improvement

A semiconductor device includes a substrate, a device layer, color filters and a passivation layer. The device overlies the substrate, and has a first surface and a second surface opposite to the first surface. The device layer includes a grid structure disposed on the second surface of the device layer, and the grid structure includes cavities. The first surface of the device layer is adjacent to the substrate. The color filters fill in the cavities. The passivation layer is disposed on the second surface of the device layer, and covers the grid structure and the color filters.

A semiconductor device with metal-doped etch stop layer therein and a method of manufacturing the same is disclosed. The method includes forming an semiconductor device with a interconnect structure that has a dielectric layer and a conductor therein, and an etch stop layer over the dielectric layer; applying a photo resist layer and patterning the photo resist layer to expose a portion of the etch stop layer on a top surface of the conductor over of the dielectric layer; and doping the exposed portion of the etch stop layer with an element to form a metal-doped etch stop layer. The formed metal-doped etch stop layer has a recess structure and functions as a conductive pad over the conductor.

Semiconductor structure and method of forming the same

A method includes performing a patterning step on a layer using a process gas. When the patterning step is performed, a signal strength is monitored, wherein the signal strength is from an emission spectrum of a compound generated from the patterning step. The compound includes an element in the patterned layer. At a time the signal strength is reduced to a pre-determined threshold value, the patterning step is stopped.

Methods for achieving width control in etching processes

The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.

Dual profile shallow trench isolation apparatus and system

A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed on the front side of the semiconductor substrate. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the dielectric layer is over a back surface of the semiconductor substrate. A metal shield is over the dielectric layer and overlapping the photo-sensitive device. A metal plug penetrates through the dielectric layer, wherein the metal plug electrically couples the metal shield to the semiconductor substrate.

Structures for grounding metal shields in backside illumination image sensor chips

A method for forming a patterned composite stack layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a blanket silicon layer. There is then formed upon the blanket silicon layer a blanket silicon containing dielectric layer. There is then formed upon the blanket silicon containing dielectric layer a patterned photoresist layer. Finally, there is etched sequentially while employing the patterned photoresist layer as a photoresist etch mask the blanket silicon containing dielectric layer and the blanket silicon layer to form a patterned composite stack layer comprising a patterned silicon containing dielectric layer coextensive with a patterned silicon layer, where the sequential etching is undertaken employing in situ in a single plasma reactor chamber or cluster of adjoining chambers a sequential plasma etch method employing a sequence of etching gas compositions which upon plasma activation perform the etching reactions with uniform linewidth dimensions and attenuated polymer residue formation and defect levels.

Plasma etch method for forming uniform linewidth residue free patterned composite silicon containing dielectric layer/silicon stack layer

A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications. When directed towards forming patterned conductor layers, such as bond pads, the method optionally employs an inert plasma treatment of a patterned conductor layer followed by an aqueous ethanolamine treatment of the patterned conductor layer prior to a first plasma treatment of the patterned conductor layer.

Method for forming corrosion inhibited conductor layer

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Tainan, Taiwan

Szu-Hung Yang