Fujitsu Semiconductor Limited

Syusaku Yamaguchi

Hiroyuki Kobayashi

Hitoshi Ikeda

Toshiya Uchida

Tatsuya Kanda

Tatsushi Otsuka

Tomohiro Kawakubo

Shinnosuke Kamata

Ayako Sato

Hidenaga Takahashi

Tetsuo Miyamoto

Yoshinobu Yamamoto

Masanori Kurita

Satoru Shirakawa

Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

Memory device, memory controller and memory system

Growing community of inventors

Kawasaki, Japan

Syusaku Yamaguchi