Other

Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Device Engineering Co., Ltd.

Syunichi Saeki

Katsutaka Kimura

Takashi Kobayashi

Hitoshi Kume

Tokuo Kure

Hideaki Kurata

Yasushi Goto

Takayuki Kawahara

Naoki Miyamoto

Yusuke Jyouno

A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regionsformed first conduction type well, floating gatesformed on semiconductor substratethrough an insulator film, control gatesformed on floating gatesthrough nitrogen-introduced silicon oxide filmand third gatesdifferent from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gatesthus formed is made lower than that of floating gates, has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

Semiconductor integrated circuit device and process for producing the same

A semiconductor integrated circuit device with third gates comprising second conduction type source/drain diffusion layer regions formed in first conduction type well , floating gates formed on semiconductor substrate through an insulator film , control gates formed on floating gates through nitrogen-introduced silicon oxide film and third gates different from the floating gates and the control gates, formed through the semiconductor substrates, the floating gates, the control gates and the insulator film, where the third gates are formed as filled in gaps between the floating gates existing in a vertical direction to word lines and channels and the height of third gates thus formed is made lower than that of floating gates , has improved reduction of memory cell size and operating speed and improved reliability after programming/erasing cycles.

This invention provides a nonvolatile semiconductor memory device having a word line, a plurality of bit lines crossing the word line, and a plurality of memory cells including MOS transistors. Each of control gates of the MOS transistors are coupled to the word line and each of drains thereof are coupled to the bit lines, respectively. Each of the MOS transistors also has a floating gate. Further, the non-volatile semiconductor memory device comprises latch circuits, first switches, a sense amplifier coupled to the plurality of bit lines in common, and second switches. The latch circuits are coupled to the plurality of bit lines through the first switches which are coupled between the plurality of bit lines and the latch circuits, respectively. The second switches are respectively coupled between the plurality of bit lines and the sense amplifier, thereby coupling the sense amplifier to the bit lines. Each of the plurality of first switches includes a MOS transistor whose source-drain path is between a corresponding one of the plurality of bit lines and a corresponding one of the latch circuits, respectively. When data is to be read from a memory cell selected out of the plurality of memory cells, the plurality of first switches are turned off and one of the second switches between the selected memory cell and the sense amplifier is turned on.

Nonvolatile semiconductor memory device

Growing community of inventors

Ome, Japan

Syunichi Saeki