Other

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Syunichi Hashimoto

Kenichi Kuroda

Masahiro Moniwa

Masayuki Kojima

Kozo Watanabe

Atsushi Ogishima

Kiyonori Ohyu

Nozomu Matsuda

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodesare formed via a gate insulating filmon the main surface of a semiconductor substrate, and on side surfaces of each of the gate electrodes there is formed a first side wall spacercomposed of silicon nitride and a second side wall spacercomposed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holesandin a self-matching manner with respect to the first side wall spacersand connecting portion is formed connecting a conductorto a bit line BL. In addition, in the N channel MISFETs Qnand Qn, and in the P channel MISFET Qpin areas other than the DRAM memory cell area, high density N-type semiconductor areasandare formed, as well as a high density P-type semiconductor areais formed in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuitry and method for manufacturing the circuitry

A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes there is formed a first side wall spacer composed of silicon nitride and a second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and connecting portion is formed connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area, high density N-type semiconductor areas and are formed, as well as a high density P-type semiconductor area is formed in a self-matching manner with respect to the second side wall spacers

It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes are formed via a gate insulating film on the main surface of a semiconductor substrate , and on side surfaces of each of the gate electrodes is formed the first side wall spacer composed of silicon nitride and the second side wall spacer composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes and in a self-matching manner with respect to the first side wall spacers and are formed connecting portion connecting a conductor to a bit line BL. In addition, in the N channel MISFETs Qn and Qn , and in the P channel MISFET Qp in areas other than the DRAM memory cell area are formed high density N-type semiconductor areas and , as well as a high density P-type semiconductor area in a self-matching manner with respect to the second side wall spacers

Semiconductor integrated circuit device and method for manufacturing the same

An electrical parallel connector comprising an integral unitary structure formed of electrical insulation hard synthetic resin and including a rectangular first connector member and a rectangular second connector member integrally connected to said first connector member by means of flexible connection strips, said first connector member having a plurality of parallel grooves extending by a substantial portion of the length of the connector member in one major surface thereof and terminating short of the opposite ends of the connector member to provide end walls which define the opposite ends of said grooves, projections on the opposite sides of said connector member for engaging the opposite sides of the second connector member, recesses in the opposite side edges of said connector member positioned adjacent to and inwardly of said projections and extending into the bottom of the adjacent groove at right angles to the groove and an intermediate recess positioned between said first mentioned recesses and extending into the bottoms of the adjacent grooves; and said second connector member having a plurality of parallel grooves extending by a substantial portion of the length of the connector member in one major surface of the connector member and terminating short of the opposite ends of the connector member to provide end walls which define the opposite ends of the grooves, the number of said grooves in the second connector member corresponding to that of said grooves in the first connector member, projections at the opposite side edges of the second connector member projecting outwardly of the major surface for engaging in said recesses in the opposite side edges of said first connector member and a recess extending between said side edge projections of the second connector member and intersecting said grooves in the second connector member at right angles thereto; further including an electrically conductive connecting blade engaging in said recesses in the first and second connector members and covered wires received in said grooves in the first and second grooves and held in position by said blade.

Electrical parallel connector

A connector for forming a series electrical connection between opposing ends of a pair of insulation-covered wires comprises a lower body portion having a longitudinal groove and a pair of upper body portions connected to and superimposable upon the lower body portion. Each of the upper body portions has a longitudinal groove for receiving and maintaining one wire end within the groove in the lower body portion. Each of the upper and lower body portions contain formations for receiving a conductive connecting piece having a pair of opposed blade portions for piercing the insulation to contact each wire end for forming a series connection. Opposing ends of the groove in the lower body portion and the outer ends of the groove in each upper body portion are formed with a thin yieldable wall for resiliently holding each wire end. Complementary means are attached to each body portion for mechanically fastening each upper body portion to the lower body portion to positively maintain proper electrical connection between the opposed wire ends.

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Hitachi, Japan

Syunichi Hashimoto