Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Syun-Ming Jang Jang

Chen-Hua Douglas Yu

Ying-Ho Chen

Tien-I Bao

Chao-Cheng Chen

Tsu Shih

Weng Chang

Chung-Long Chang

Yung-Cheng Lu

Chu-Yun Fu

Tze-Liang Lee

Jih-Churng Twu

Ming-Hsing Tsai

Hung-Wen Su

Lain-Jong Li

Wen-Chih Chiou

Chung-Shi Liu

Mong-Song Liang

Chii-Horng Li

Jyu-Horng Shieh

Liang-Yin Chen

Zhen-Cheng Wu

Huicheng Chang

Ming-Ching Chang

Hsien-Ming Lee

Horng-Huei Tseng

Carlos H Diaz

Ming-Hsi Yeh

Chih-Han Lin

Chung-Chi Ko

Ming-Hua Yu

Da-Yuan Lee

Su-Hao Liu

Chen-Yuan Kao

Kuei-Yu Kao

Minghsing Tsai

Hung-Chin Chung

Shau-Lin Shue

Yee-Chia Yeo

Chun-Hsiung Lin

Mao-Lin Huang

Chun-Chieh Lin

Sheng-Liang Pan

Chien-Hsun Wang

Chi On Chui

Ziwei Fang

Anthony Yen

Shih-Yao Lin

Tai-Chun Huang

Tsang-Jiuh Wu

Chih-Yuan Ting

Chia-Cheng Chen

Tsan-Chun Wang

Kai-Hsuan Lee

Xiong-Fei Yu

Chien-An Chen

Shen-Nan Lee

Yi-Ming Sheu

Kuo-Ju Chen

Po-Cheng Shih

Shwang-Ming Jeng

Ching-Hua Hsieh

Chenming Hu

Fu-Liang Yang

Keng-Chu Lin

Hun-Jan Tao

Jeng-Horng Chen

Ryan Chia-Jen Chen

Chan-Lon Yang

Shu-Yuan Ku

Li-Ting Wang

Shiang-Bau Wang

Chih-Tang Peng

Shing-Chyang Pan

Ya-Lien Lee

Cheng-Chung Lin

Wen-Yen Chen

Ying-Tsung Chen

Chia-Shiung Tsai

Sai-Hooi Yeong

Chi-Feng Huang

Chih-Hsin Ko

Ying-Lang Wang

Kuo-Hua Pan

Pei-Ren Jeng

Pang-Yen Tsai

Hung-Chang Hsieh

Yih-Ann Lin

Ming-Huan Tsai

Chia-Ying Lee

Yi-Hung Lin

Min Cao

Ming-Chung Liang

Harry Hak-Lay Chuang

Shun-Liang Hsu

Sheng-Hsuan Lin

Yuan-Hung Chiu

Chih-Hsien Lin

Szu-An Wu

Chih-Hsiang Yao

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Device having an air gap adjacent to a contact plug and covered by a doped dielectric layer

A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.

Patterning interconnects and other structures by photo-sensitizing method

Embodiments described herein relate to plasma processes. A plasma process includes generating a plasma containing negatively charged oxygen ions. A substrate is exposed to the plasma. The substrate is disposed on a pedestal while being exposed to the plasma. While exposing the substrate to the plasma, a negative direct current (DC) bias voltage is applied to the pedestal to repel the negatively charged oxygen ions from the substrate.

DC bias in plasma process

The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Semiconductor device with profiled work-function metal gate electrode and method of making

A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Chemical direct pattern plating method

Method of manufacturing a FinFET by implanting a dielectric with a dopant

A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.

Method of fabricating a source/drain recess in a semiconductor device

A method includes forming a gate stack over a first semiconductor region, removing a second portion of the first semiconductor region on a side of the gate stack to form a recess, growing a second semiconductor region starting from the recess, implanting the second semiconductor region with an impurity, and performing a melting laser anneal on the second semiconductor region. A first portion of the second semiconductor region is molten during the melting laser anneal, and a second and a third portion of the second semiconductor region on opposite sides of the first portion are un-molten.

Melting laser anneal of epitaxy regions

Semiconductor device having a contact plug with an air gap spacer

Growing community of inventors

Hsinchu, Taiwan

Syun-Ming Jang Jang