Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Syuji Kato

Akinori Shinmyo

Toru Iwata

Ryogo Yanagisawa

Masami Funabashi

Shinya Murakami

A clock recovery system includes: a sampler that samples reception data with 2N phase clocks and outputs 2N&#xd7;M sampling signals; a data selector that selects n&#xd7;M recovery signals from the 2N&#xd7;M sampling signals and outputs the n&#xd7;M recovery signals; a phase comparator that outputs, for each of the n&#xd7;M recovery signals, a phase comparison signal based on the recovery signal, a first sampling signal sampled with a first clock that leads by one or more phases from a sampling clock, and a second sampling signal sampled with a second clock that delays by one or more phases from the sampling clock; a controller that designates n based on a data rate of the reception data; and a multiphase clock generator that generates and outputs the 2N phase clocks based on the phase comparison signal and n.

Clock recovery system

A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

Noise cancelling circuit and data transmission circuit

An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.

Video input device and video display system

An input clock dividing unit frequency-divides an input clock, and an input clock multiplying unit frequency-multiplies the input clock. An operation clock selecting unit selects the frequency-divided clock when the input clock is fast and selects the frequency-multiplied clock when the input clock is slow, based on the frequency detection result of frequency detecting unit. The operation clock selecting unit then outputs the selected clock to a phase comparing unit as an operation clock. The phase comparing unit operates according to the frequency-divided or frequency-multiplied clock, and controls an oscillating unit so that the phase difference between a reference signal and a comparison signal becomes zero. The phase of an output clock is thus caused to track the phase of the reference signal.

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Osaka, Japan

Syuji Kato