Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Ebara Corporation

Syuichi Ueno

Takashi Kuroi

Katsuyuki Horita

Katsuomi Shiozawa

Yasuyoshi Itoh

Tadamasa Hayashi

Toyoshi Mizushima

Masashi Fukuhara

Jyunichi Yamaji

Toshiyuki Koya

Takashi Ohtu

A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

Semiconductor device including impurity layer having continuous portions formed at different depths and method of manufacturing the same

A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N -type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

A semiconductor device and manufacturing method capable of forming shallow extension regions in insulated-gate transistors. A side wall material containing about 1 to 20% of phosphorus, such as PSG, is deposited on the sides of an opening to a film thickness of tens of nanometers to about 100 nm and etched back to form phosphorus-containing side walls respectively adjacent to boron-containing side walls. An interlayer insulating film of silicon nitride etc. is then formed on the silicon nitride film. A thermal process performed during formation of the interlayer insulating film forms N-type extension regions in the NMOS region through a diffusion where phosphorus contained in the phosphorus-containing side walls serves as the diffusion source and P-type extension region in the PMOS region through a diffusion where boron contained in the boron-containing side walls serves as the diffusion source.

Semiconductor device manufacturing method and semiconductor device

A heat transfer material for heating and heating unit and heating apparatus using the same material, wherein the heat transfer material comprises a substrate 2 and an electrical insulating layer 4 as a first layer, an electrically conductive layer 5 entirely or partially provided as a second layer, and a heat insulating layer 6 as a third layer, all of which are formed in turn on the substrate 2, whereby a heat transfer material for heating which is capable of insulating a substance to be heated and highly heat efficiency uniformly heating and which has rapid thermal response is obtained.

Heat transfer material for heating and heating unit and heating

Growing community of inventors

Tokyo, Japan

Syuichi Ueno