Fujitsu Corporation

Fujitsu Semiconductor Limited

Syuichi Saito

Hajime Sato

Akihiro Iwase

Satoru Kawamoto

Koji Okada

Isamu Kobayashi

A spread spectrum clock generation circuit and a controlling method thereof are disclosed, which provide clocks having less jitter and ideal spread spectrum and enable a reduction in circuit scale and in power consumption. To this end, a current control type modulatoris equipped with a current source Ia (current). A charger unit CGa and a discharger unit DGa are designed such that currents i,andare allowed to flow, for example, by properly setting the sizes of transistors. Modulation cycles CIa to CIIIa are repeated and an output code is generated from a switching control circuitaccording to each modulation cycle. A switching unit SSa is controlled according to the output code, thereby charging or discharging a capacitor element Cwith a charge/discharge current CDI corresponding to the output code. Hence, charge amounts and discharge amounts for all the modulation cycles CIa to CIIIa have the same value, i.e.,[A&#xb7;clock].

Spread spectrum clock generation circuit and a method of controlling thereof

A voltage generator circuit which is capable of preventing the generation of a through current in a transition to a power-down mode to reduce current consumption. The voltage generator circuit includes a voltage generator activated by a reference voltage to generate an output voltage. A reference voltage clamp circuit is coupled to the voltage generator for clamping the reference voltage to a first voltage in response to a power-down signal to deactivate the voltage generator. An output voltage clamp circuit is coupled to the voltage generator for clamping the output voltage to a second voltage. A control circuit is coupled to the output voltage clamp circuit for enabling the output voltage clamp circuit after the voltage generator is deactivated in response to the power-down signal.

Voltage generator circuit and method for controlling thereof

A semiconductor testing circuit being arranged for testing a semiconductor storage device, and having a simple construction and a great number of executable test patterns. Counters designate portions of a write/read address by count values outputted from the counters, respectively, where each of the portions is comprised of one bit or a plurality of successive bits. A switching circuit selectively outputs counter-control signals for individually controlling operations of the counters. Each of the counter-control signals is a common counter-control signal commonly used for the counters or the most significant bit of one of the portions outputted from a first one of the counters other than a second one of the counters for which the counter-control signal is outputted. Thus, it is possible to change assignment of the write/read address to the count values of the counters.

Semiconductor testing circuit, semiconductor storage device, and semiconductor testing method

An oscillator circuit which generates an oscillator signal that ensures the generation of a stable internal supply voltage. The oscillator circuit has a periodic circuit which includes a switch circuit. A method of controlling the oscillator circuit includes the steps of operating the periodic circuit using the switch circuit in response to a first control signal when the first control signal is in a first state to generate a first oscillator signal having a first frequency, and operating the periodic circuit using the switch circuit in response to a second control signal when the first control signal is in a second state to generate a second oscillator signal having a period synchronized to a period of the second control signal having a second frequency.

Oscillator circuit of internal power generator circuit and control method thereof

A semiconductor memory device includes a memory cell array having memory cells located at the intersections of bit lines and word lines. Driver circuits are connected to groups of the word lines. A first decoder circuit is connected to the driver circuits to selectively activate them. A second decoder circuit is also connected to the driver circuits to activate selected ones of the word lines. In response to a test signal, the first decoder circuit simultaneously activates all of the driver circuits and the second decoder circuit activates the selected ones of the word lines.

Semiconductor memory device with a test mode

A semiconductor device that optimally controls a current supply of internal power supply voltage generation circuits in accordance with the number of banks that are simultaneously activated. A control circuit adjusts the activated number of internal power supply voltage generation circuits in response to activation signals of the banks.

Semiconductor device and method for generating internal power supply voltage

An internal power supply auxiliary circuit supplies a current to a power generator circuit. A pulse signal generator receives an input signal and outputs a first control signal. A driver circuit connected to the pulse signal generator receives the first control signal, an external supply voltage and a source voltage, and generates a drive pulse signal. A current supply driver circuit receives the drive pulse signal and the external supply voltage and outputs the supply current to the power generator circuit. A gate voltage regulator circuit connected to the driver circuit receives a reference voltage and produces the source voltage. The gate voltage regulator causes the source voltage to substantially match the reference voltage so that the current supplied to the power generator circuit does not exceed a predetermined value.

Power supply auxiliary circuit

A voltage conversion circuit has an improved power efficiency and a lower power consumption is described. The voltage conversion circuit includes a plurality of voltage conversion cells, each of which includes a capacitor element. A switch circuit is connected to the plurality of voltage conversion cells to selectively switch between parallel connection of a plurality of voltage conversion cells and serial connection of a plurality of voltage conversion cells. A control circuit is connected to the switch circuit to control the switch circuit to selectively perform a first voltage conversion of an input voltage by the plurality of parallel-connected voltage conversion cells and a second voltage conversion of the input voltage by the plurality of series-connected voltage conversion cells.

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Kasugai, Japan

Syuichi Saito