Sanyo Electric Co., Ltd.

Nippon Hoso' Kyokai

Syugo Yamashita

Toshiya Iinuma

Haruhiko Murata

Yoshikazu Tomida

Osamu Yamada

Masayuki Takada

Yukio Mori

Seiji Okada

Susumu Tanase

Toru Kuroda

Masahiko Yoshiyama

Tadashi Isobe

Akihiro Maenaka

Kazuhiro Kimura

Toshiyuki Okino

Takahiko Masumoto

Hiroshi Kaneko

Tetsuo Mise

Minoru Honda

Hidekazu Uchida

Takayuki Mori

Toshihiro Kubo

Terumasa Tokumoto

Kanzi Ihara

Mitsuo Nakashima

There are provided hue detecting means for detecting a hue component for each pixel from a first color difference signal R&#x2212;Y and a second color difference signal B&#x2212;Y, and gain controlling means for controlling for each pixel a gain for arbitrarily selected one of or an arbitrary combination of a luminance signal, a first color difference signal R&#x2212;Y, and a second color difference signal B&#x2212;Y depending on the detected hue component for each pixel.

Tone correcting circuit and hue correcting circuit

Disclosed is an interpolation pixel value determining method for dividing a unit region including the contour of an object into reference unit sections for each line along a predetermined direction, to find, using a region interposed between the two reference unit sections as an interpolation unit section, an interpolation pixel value in the interpolation unit section, in which a luminance total and a center of gravity are calculated in each of the two reference unit sections with the interpolation unit section interposed therebetween, the estimated values of a luminance total and a center of gravity in the interpolation unit section are found from the luminance totals and the centers of gravity in the two reference unit sections, and each of interpolation pixel values in the interpolation unit section is determined such that the luminance total and the center of gravity in the interpolation unit section are respectively values close to the estimated values.

Interpolation pixel value determining method

There is provided parallax correction means for correcting a parallax for each area calculated by parallax calculation means in accordance with the magnitude of a motion vector for the area detected by motion vector detection means in order to prevent the three-dimensional effect of a conversion video from greatly differing depending on an input video when the MTD method and the CID method are simultaneously used. When a depth estimate is converted into a parallax, the depth estimate is subjected to distance scale conversion in order to suppress the distortion of the conversion image, to find a tentative target phase for each parallax calculation area, and a dynamic range in which a phase difference between the parallax calculation areas is within a distortion allowable range is searched for and is subjected to distance scale conversion, to find a tentative target phase, which operations are repeated.

Device and method for converting two-dimensional video to three-dimensional video

In a telecine converting method for converting a video in a movie film composed of 24 frames per second into a video signal composed of 60 frames per second, a telecine converting method is characterized in that in order that respective integration values of display time periods of frame videos in the movie film become equal after the telecine conversion, used as a video in the predetermined frame after the conversion is an interpolated video obtained by interpolating the frame videos ahead of and behind the video in the movie film.

Telecine converting method

A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.

Error correction device

In the present invention, two-dimensional images are converted into three-dimensional images by producing from a two-dimensional image signal a main image signal and a sub-image signal delayed from the main image signal. A field delay indicating how many fields are there from a field corresponding to the main image signal to a field corresponding to the sub-image signal is changed depending on the speed of the horizontal movement of the main image signal. The upper limit of the field delay is determined on the basis of vertical components of motion vectors detected from the main image signal. The field delay is so determined that it is not more than the determined upper limit.

Method of converting two-dimensional images into three-dimensional images

An error correcting decoder includes a flag memory (20) which stores a flag indicative of a success of an error correction for a bit. When a column direction error correction is to be performed, if a flag for a bit indicates a success, no error correction is performed for the bit. That is, an output of a majority logic circuit (78) is forcedly made invalid. In performing the column direction error correction, if the number of success packets in a first-time row direction error correction is smaller than a predetermined value and if the number of bits corrected by the column direction error correction becomes equal to or larger than a predetermined number, it is deemed as that the column direction error correction is unsuccessful. In performing a second-time row direction error correction, when a threshold value is equal to or larger than a predetermined value, the majority logic circuit determines with referring to a result of the column direction error correction, but without referring to the result when the threshold value is smaller than the predetermined value.

Error correcting decoder

A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).

Frame-synchronous reproducing circuit

An error rate measuring apparatus includes a demodulator, and data from the demodulator is applied to a decoding circuit in which an error bit number is evaluated for each of a BIC portion and a packet portion. In the BIC portion, if a synchronization is settled, the error bit number is evaluated by comparing received BICs and a predetermined BIC pattern, and if the synchronization is not settled, the error bit number is determined as eight (8) bits. In the packet portion, if a frame synchronization is settled and decoding is successful, the error bit number is calculated by comparing data before decoding and data after decoding with each other. If the frame synchronization is settled but the decoding is unsuccessful, a presumed error bit number is set according to the number of packets being decoded successfully in a first time horizontal direction, and if the frame synchronization is not settled, a predetermined error bit number is set. In each of the BIC portion and the packet portion, a bit error rate is calculated on the basis of the error bit number for each measurement range, and displayed on a monitor.

Error rate measuring apparatus

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Hirakata, Japan

Syugo Yamashita