Psiquantum Corp.

Eliyan Corporation

Qualcomm Incorporated

Syrus Ziai

Faraz Najafi

Ramin Farjadrad

Peng Zou

Mark G Thompson

Vimal Kumar Kamineni

Qiaodan Jin Stone

Damien Bonneau

George Kovall

Vitor Riseti Manfrinato

Chia-Jung Chung

Curtis McAllister

Gang Ren

Mark Thompson

Curtis Roger McAllister

Xijian Lin

Kevin Donnelly

Joseph Dibene

Curtis Roger Mcallister

A physical layer interconnect between chips/chiplets provides high bandwidth communication with low power requirements using an organic substrate such as a printed circuit board. An interface between first and second chiplets uses a separate chiplet, or a combination logic die and interconnect interface, interfacing with the interconnect. A connection between a computing device and a memory can be longer, allowing the computing device to be coupled to more memories, expansion slots, or external connections. The interconnect can route memory commands between computing devices and memories, allowing multiple and different computing devices to be coupled to each other or to multiple and different memories. The memories can perform in-memory computing using chiplets coupled thereto. The interconnect couples to possibly different computing devices and possibly different memories, such as in a rack configuration, including CPUs or GPUs. The specialized processing devices can include one or more TPUs or VPUs.

Complex system-in-package architectures leveraging high-bandwidth long-reach die-to-die connectivity over package substrates

A method includes receiving input light having an input wavelength in a first optical resonator for causing resonance of the input light in the first optical resonator. The first optical resonator includes a non-linear optical medium. The method also includes converting at least a portion of the input light to a combination of first output light having a first output wavelength that is different from the input wavelength and second output light having a second output wavelength that is different from the input wavelength and the first output wavelength by passing the input light through the non-linear optical medium. The method further includes causing resonance of the first output light and the second output light in a second optical resonator. A portion of the first optical resonator is coupled to a portion of the second optical resonator.

Photon sources with multiple cavities for generation of individual photons

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a chiplet-based multi-chip module (MCM) is disclosed. The chiplet-based MCM includes a package substrate and a first processing integrated circuit (IC) chiplet disposed on the package substrate. A second processing IC chiplet is disposed on the package substrate. At least one first row multi-port memory chiplet is disposed on the package substrate and coupled between the first processing IC chiplet and the second IC processing chiplet. Data transfers between the first processing IC chiplet and a destination IC chiplet are routed through the at least one first row multi-port memory chiplet.

Multi-chip module (MCM) with multi-port unified memory

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.

Vertically integrated device stack including system on chip and power management integrated circuit

A superconductor device includes a barrier layer over a substrate including silicon, the barrier layer including silicon and nitrogen, and a seed layer for a superconductor layer over the barrier layer, the seed layer including aluminum and nitrogen, and superconductor layer over the seed layer, the superconductor layer including a layer of a superconductor material, the barrier layer serving as an oxidation barrier between the layer superconductor material and the substrate. In some embodiments, the superconductor device includes a waveguide and a metal contact at a sufficient distance from the waveguide to prevent optical coupling between the metal contact and the waveguide.

Superconducting nanowire single photon detector and method of fabrication thereof

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chip disposed on the common substrate. The first IC chip includes a first memory interface. A second IC chip is disposed on the common substrate and includes a second memory interface. A first memory device is disposed on the common substrate and includes memory and a first port coupled to the memory. The first port is configured for communicating with the first memory interface of the first IC chip. A second port is coupled to the memory and communicates with the second memory interface of the second IC chip. In-memory processing circuitry is coupled to the memory and controls transactions between the first memory device and the first and second IC chips.

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes memory control circuitry for controlling at least one memory die of a first memory type. A die-to-die (D2D) interface circuit couples to a host IC chiplet. The D2D interface circuit includes input/output (I/O) circuitry for coupling to multiple signaling lanes for transferring information packets with the host IC chiplet.

Universal memory interface utilizing die-to-die (D2D) interfaces between chiplets

A computing device performs both read/write operations concurrently to a memory. Queues for read or write operations are maintained on the memory, allowing the computing device to issue concurrent read/write commands, without complex ordering/buffering circuitry. For a read operation, the memory receives the read command and buffers it in a priority order assigned thereto. The memory can perform the read command and respond with the requested response on a data bus disposed to communicate read data. For a write operation, the memory receives the write command and buffers it for processing in a priority order for that command, such as for relatively immediate processing. The memory can perform the write command using write data on a separate data bus disposed to communication write data.

Architecture for DRAM control optimization using simultaneous bidirectional memory interfaces

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes at least one memory die of a first memory type. Memory control circuitry is coupled to the at least one memory die. An interface circuit is for coupling to a host IC chiplet. The interface circuit includes data input/output (I/O) circuitry for coupling to multiple data lanes. Link directional control circuitry selects, for a first memory transaction, a first subset of the multiple data lanes to transfer data between the memory chiplet and the host IC chiplet.

Universal memory interface with dynamic bidirectional data transfers

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a package substrate and an integrated circuit (IC) processor chip disposed on the package substrate. The IC processor chip includes a data interface configured to support N channels. A scalable high bandwidth memory (HBM) is coupled to the IC processor chip. The scalable HBM includes a first HBM device disposed on the package substrate with a first primary data interface that supports a first set of N/2 data channels and a first data transfer rate. A second HBM device is disposed on the package substrate and supports a second set of N/2 data channels and a second data transfer rate. The first HBM device and the second HBM device are configured to collectively support the full N channels and an aggregate data rate that is a sum of the first data rate and the second data rate.

Multi-chip module (MCM) with scalable high bandwidth memory

A system includes a plurality of superconducting wires connected in parallel with one another. The plurality of superconducting wires includes a first superconducting wire and a second superconducting wire. The plurality of superconducting wires are configured to, while receiving a bias current provided to the parallel combination of the plurality of superconducting wires, operate in a superconducting state in the absence of a trigger current. The first superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to receiving the trigger current. The second superconducting wire is configured to, while receiving the bias current, transition to a non-superconducting state in response to the first superconducting wire transitioning to the non-superconducting state.

Superconducting signal amplifier

An electronic device has a power rail that is driven by voltage regulators and provides a rail voltage. Each voltage regulator has an output interface electrically coupled to the power rail to deliver up to a predefined regulator current to the power rail. In each voltage regulator, a voltage regulator controller has an input coupled to the output interface by a feedback path and controls a drive path coupled to the output interface. A bypass unit is coupled to the drive path and voltage regulator controller and operates in a standby mode or an operational mode. In the standby mode, the bypass unit bypasses the feedback path and the respective voltage regulator does not deliver current to the power rail, while in the operational mode, the bypass unit does not bypass the feedback path and the respective voltage regulator delivers up to the predefined regulator current to the power rail.

Management of voltage regulator units in field programmable arrays

A multi-chip module (MCM) includes a common substrate and first and second integrated circuit (IC) chips disposed on the common substrate. The first integrated circuit (IC) chip includes a first interface circuit disposed proximate a first edge of the first IC chip and a second interface circuit disposed proximate the first edge of the first IC chip. A first chiplet couples to the first interface circuit via a first link. A second chiplet couples to the second interface circuit via a second link. A first position of the first chiplet with respect to the first IC chip is staggered in a longitudinal dimension relative to a second position of the second chiplet with respect to the first IC chip.

Growing community of inventors

Los Altos, CA, United States of America

Syrus Ziai