Bull S.a.

Bull Sas

Sylvie Lesmanne

Alain Boudou

Christian Bernard

Ghassan Chehaibar

Pamphile Koumou

Axel Poudes

Anne Kasynski

Managing the end-to-end reliability in the delivery with acknowledgment of data from a source node () to a group of destination nodes (-), including the steps of marking messages () transmitted from the source node (); upon transmission of a message, incrementation of an overall sequence number; identification of the overall sequence number of a message transmitted by which the source node has not received an acknowledgment; and calculation of the difference between the overall sequence number of the next message to be transmitted and the identified overall sequence number. If the calculated difference is equal to a predefined threshold, suspend the transmission of messages from the source node () to the group of destination nodes (-) and conclude the presence of an error in the delivery of data.

Method and system for flow control

A coherence controller is included in a module which includes a plurality of multiprocessor units, each of which contains a main memory and processors equipped with respective cache memories. The module may be one of a plurality of similarly constructed modules connected by a router or other type of switching device. The coherence controller in each module includes a cache filter directory having a first filter directory for guaranteeing coherence between the local main memory and the cache memory in each of the processors of the module, and an external port connected to at least one of the other modules. The cache filter directory also includes a complementary filter directory, which tracks locations of lines or blocks of the local main memory copied from the module into other modules, and for guaranteeing coherence between the local main memory and the cache in each of the processors of the module and the other modules.

Coherence controller for a multiprocessor system, module, and multiprocessor system with a multimodule architecture incorporating such a controller

The process for exchanges between the levels in a hierarchy of memories comprising at least one intermediate level in the hierarchy linked to a higher level in the hierarchy and to a lower level in the hierarchy, with each level in the hierarchy being divided into memories (3, 5, 6) which are in turn divided into blocks (10) containing information (11) associated with addresses (Ad), with the blocks of the memories on the higher level and on the intermediate level in the hierarchy containing copies of the information held in the blocks at the corresponding addresses on the lower level in the hierarchy, and during a modification of a piece of information in a block (10.32) of a memory on the higher level in the hierarchy, invalidating at least some of the information at the corresponding addresses of other memories on the higher level in the hierarchy, and managing an update or an invalidation of the information at the corresponding addresses on the intermediate level and the lower level in the hierarchy, depending on the usefulness of the update.

Process for managing a hierarcy of memories

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Les Clayes Sous Bois, France

Sylvie Lesmanne