International Business Machines Corporation

Sylvain Leforestier

Dominique M Omet

There is described a double stage sense amplifier (4) in bipolar technology achieving very high speed operation without saturation or connection problems. For each memory cell column of the computer member system (1), a first stage or column sense stage (4.1) amplifies the differential input signal (V) produced on the pair of bit lines (BLL, BLR) according to the information read from one CMOS memory cell of the memory cell array (3.1) to provide a first differential output signal (V1) available at output terminals (10.1, 10.2). The output terminals of all the first stage (4.1 to 4.n) are connected to a first-data out bus comprised of the data lines (DLC1, DLT1). A second stage or final stage (4') amplifies the first differential output signal developed on the data lines to provide a second differential output signal (V2) at output terminals (17.1, 17.2). The second stage of the common base amplifier type is comprised of two transistors (T9, T10). The base electrodes of these transistors are connected to a reference voltage generator (13) which supplies a reference voltage VREF such as VREF=VH-1.5 VBE. This special value greatly helps both first and second stages not to saturate and in addition, minimizes the sensibility of the sense amplifier to the connection of additional memory cell columns on the data lines (DLC1, DLT1). Both stages are provided with various antisaturation circuits (9, 11.1; 11.2, 16.1, 16.2) which cooperate with the reference voltage generator to keep any transistor far from saturation.

Double stage bipolar sense amplifier for BICMOS SRAMS with a common base

A two stage address decoder circuit (AD) for 1/64 decode operation is disclosed which operates at high speed with low power consumption. Briefly stated, the circuit includes a first stage comprised of two predecoder circuits operable to develop predecoded output signals in response to input address signals and corresponding inverted address signals. Each predecoder circuit consists of a lower power high speed Differential Cascode Current Switch tree with its associated current source. The second or final decode stage is comprised of a plurality of final decoding circuits. Each final circuit consisting of a 2 way OR gate dynamically activated through a switched current source. The inputs of the 2 way OR gate are connected to one pair of the predecoded output signals. Final decoder circuits provide final decoded output signals which drive the word lines of a memory cell array. The switched current source is triggered by a control signal supplied by a clock generator (CG) so that the final decode circuits consume power only when the control signal is active.

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Le Chenay, France

Sylvain Leforestier