Bull Sas

Bull

Sylvain Jeaugey

Philippe Couvee

Zoltan Menyhart

Jean-Jacques Pairault

Simon Derr

Frederic Temporelli

Saïd Derradji

Frédéric Temporelli

Angelo Solinas

Jordan Chicheportiche

Jean Olivier Gerphagnon

A method for monitoring the operation of an IT infrastructure including a plurality of calculation nodes, includes selecting calculation nodes for performing a calculation, performing the calculation via the selected calculation nodes, attributing, via the sequencer, a score to each one of the calculation nodes having participated in the calculation performed, with each score reflecting a difference between a measured operating parameter of the calculation node for which the score is attributed and a reference operating parameter of the calculation node for which the score is attributed, verifying the operation of the calculation nodes having participated in the calculation performed, the verification being carried out using scores attributed to the calculation nodes having participated in the calculation.

Method and sequencer for detecting a malfunction occurring in a high performance computer

A data-processing system (DTS) includes a central hardware unit (CPU) and an additional hardware unit (HW), the central hardware unit (CPU) being adapted to execute a task by a processing thread (T), and to trigger offloading of execution of a first part (P, P, P) of the task to the additional hardware unit (HW); and wherein the additional hardware unit is adapted to call on functionalities of the central hardware unit (CPU), triggered by the first part, and the central hardware unit (CPU) executes a second part (P) of the task forming a sub-part of the first part by a service processing thread (T).

Double processing offloading to additional and central processing units

A computer system for managing the execution of threads including at least one central processing unit which performs interleaved execution of a plurality of threads throughout a plurality of virtual processors from said same central processing unit, and a handler for distributing the execution of the threads throughout the virtual processors. The computer system further includes means for classifying threads to be executed according to several predetermined types, and the handler for distributing the execution of threads directs each thread to be executed to a virtual processor according to the type thereof.

System and method for managing the interleaved execution of threads

A computer device with synchronization barrier including a memory and a processing unit capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, the blocks being associated by groups in successive work steps. The device further includes a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.

Physical manager of synchronization barrier between multiple processes

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Meylan, France

Sylvain Jeaugey