Advanced Micro Devices Corporation

Ati Technologies Ulc

Syed Zohaib M Gilani

Michael Mantor

John Kalamatianos

Greg Sadowski

Timour T Paltashev

Bin He

Jiasheng Chen

YunXiao Zou

Qingcheng Wang

A method and apparatus of asynchronous scheduling in a graphics device includes sending one or more instructions from an instruction scheduler to one or more instruction first-in/first-out (FIFO) devices. An instruction in the one or more FIFO devices is selected for execution by a single-instruction/multiple-data (SIMD) pipeline unit. It is determined whether all operands for the selected instruction are available for execution of the instruction, and if all the operands are available, the selected instruction is executed on the SIMD pipeline unit. The self-timed arithmetic pipeline unit (SIMD pipeline unit) is effectively encapsulated in a synchronous, (e.g., clocked by global clock), scheduler and register file environment.

Method and apparatus for asynchronous scheduling

Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.

Method and processing apparatus for gating redundant threads

At an instruction pipeline of a data processor, pipeline resource conflicts are detected by setting, for each executing instruction, one or more assignment indicators to indicate which pipeline resources are to be utilized for executing the instruction. The instruction pipeline detects a pipeline resource conflict if an instruction is assigned a pipeline resource for which the assignment indicator is set. In addition, for selected pipeline resources, such as registers in a register file, the instruction pipeline can detect a pipeline resource conflict if more than one instruction attempts to access the pipeline resource when the assignment indicator for the resource is set. In response to detecting a pipeline resource conflict, the instruction pipeline is flushed and returned to a checkpointed state, thereby protecting the instruction pipeline from architectural state errors.

Error protection for pipeline resources

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Markham, Canada

Syed Zohaib M Gilani