Signetics

Syed T Mahmud

Singh B Yalamanchili

A non-inverting low power high speed bootstrapped buffer having a depletion mode FET device which senses a rising voltage triggers the bootstrap of a high capacitance node isolated from the input. Heavy output loading can be isolated from the bootstrap node. High resistance devices are used to make a fully static circuit.

Non-inverting, low power, high speed bootstrapped buffer

A ratioless, zero d.c. power dissipating FET programmable logic array including a column boost capacitor for maintaining the columns of selected AND array transistors at approximately their precharged voltage while their associated OR array transistors are being evaluated.

Ratioless FET programmable logic array

A flip-flop with a built-in enable function realized by the addition of two transistors between the trigger circuit and the output nodes of the flip-flop. This embodiment of the enable function causes no increase in power dissipation and may be used in any type of flip-flop.

Flip-flop circuit with built-in enable function

A read resettable memory circuit contains a flip-flop circuit (10) consisting of a flip-flop (FF) and an edge-triggered control circuit (CC) and a fall-through latch (16). The control circuit sets the flip-flop in response to a selected edge transition in a first clock (.0..sub.1) when an appropriate external logical set signal (S) is received and resets the flip-flop in response to a selected edge transition in a second clock (.0..sub.2) when an appropriate feedback logical reset signal (R) is received. The latch provides the reset signal at a value corresponding to the current logic state of the flip-flop during each period running from the selected edge transition of the second clock to its opposite edge transition and at a value corresponding to the logic state of the flip-flop that exists just before each opposite edge transition of the second clock during each remaining following period.

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Los Gatos, CA, United States of America

Syed T Mahmud