Freescale Semiconductor,inc.

Syed Shakir Iqbal

Gaurav Gupta

Kumar Abhishek

Gaurav Goyal

Gourav Kapoor

A configurable delay cell for an integrated circuit includes a CMOS inverter and first through fourth transistors. A drain of the third transistor is connected to a drain of the fourth transistor for generating an output signal. A connection between an output terminal of the CMOS inverter and a source of the first transistor, a connection between the output terminal of the CMOS inverter and a drain of the second transistor, and a connection between the source of the first transistor and the drain of the second transistor are configurable, using an electronic design automation (EDA) tool, for achieving first, second, third, fourth, and fifth delay values. The resulting delay value can be programmed by making changes only in one or more of the metal layers of the integrated circuit.

Configurable delay cell

A scannable flip-flop circuit and method for low power scan operation are provided. The scannable flip-flop includes a flip-flop for receiving an input signal, and for generating a flip-flop output signal. The scannable flip-flop also includes a voltage selection circuit coupled to the flip-flop. The voltage selection circuit supplies a first voltage to the flip-flop during a first state of a voltage selection signal, and supplies a second voltage to the flip-flop during a second state of the voltage selection signal. A series of scannable flip-flops may be arranged in a scan chain for testing during a scan test mode.

Growing community of inventors

New Delhi, India

Syed Shakir Iqbal