Lsi Logic Corporation

Cirrus Logic Inc.

Sirf Technology, Inc.

Syed Khalid Azim

David R Welland

Caiyi Wang

Douglas R Holberg

Nadi Rafik Itani

Sandra Marie Johnson

Brannon Craig Harris

Alan Wayne Hansford

Keven Hui

Ash Prabala

Shih-chung Chao

Venkat Yadavalli

Systems and methods for obtaining corrected time information in a GPS-enabled device connected to a mobile handset via a short-range wireless network, such as a Bluetooth&#x2122; Piconet&#x2122;. The mobile handset includes a GPS time and a network clock synchronized with a network clock in a short-range wireless network interface in the GPS-enabled device. The GPS-enabled device may send requests for time information to the mobile handset. The mobile handset receives the request and latches the network clock time and the GPS time. The captured network clock time and GPS times are sent to the GPS-enabled device in response to the request. The GPS-enabled device subtracts the captured network clock time from its own network clock time and adds the difference to the captured GPS time to obtain a corrected GPS time.

System and method for providing aiding information to a satellite positioning system receiver over short-range wireless connections

An image processor system for a charge coupled device (CCD) or CMOS imaging system includes a correlated double sample and variable gain (CDSVGA) circuit for receiving data from a CCD system and an automatic gain control (AGC) circuit which first controls gain by adjusting said CCD system and then for yet a higher gain level makes gain adjustments in said CDSVGA circuit AND a digital gain circuit to produce a combined target gain level. A processing system for an imager device includes a camera system for producing an imager signal, a correlated double sample (CDS) circuit for receiving data from an imager, a variable gain amplifier (VGA), an analog-to-digital converter (ADC) coupled to said CDS circuit, a digital gain circuit (DGC) coupled to said ADC, and an automatic gain control (AGC) circuit coupled to said DGC for controlling the CDS circuit and the DGC. The processing circuitry includes an analog front end and a digital signal processing system for capturing full motion video and outputting a CCIR 601 4:2:2 YCrCb video data output for presentation on a user selected display.

Correlated double sampling variable gain amplifier circuit for use in a digital camera

A mechanism for synchronizing a multiple-circuit system, includes (a) selecting a master circuit from a plurality of circuits, the remaining circuits including at least one slave circuit, (b) receiving, at each of the plurality of circuits, input data and a local clock signal associated with the input data, (d) generating at least one control signal at the master circuit using the local clock signal of the master circuit, (e) outputting the control signal from the master circuit, (f) forwarding the control signal to the slave circuit(s), (g) looping back the control signal to the master circuit, (h) processing the input data at the slave circuit(s) using the forwarded control signal, (i) processing the input data at the master circuit using the looped-back control signal, and (j) outputting the processed data from each of the plurality of circuits.

System and method for synchronizing a selected master circuit with a slave circuit by receiving and forwarding a control signal between the circuits and operating the circuits based on their received control signal

A double data rate (DDR) circuit for testing of a high speed DDR interface using single clock edge triggered tester data. The DDR testing circuit includes a first register, a second register, and a multiplexer (MUX). A clock signal is fed to the first register and the MUX. The inverse of the clock signal is fed to the second register. A tester data signal is fed to the first register which generates a latched tester data signal which is fed to the MUX. The inverse of the latched tester data signal is fed to the second register which generates a transformed tester data signal which is fed to the MUX. The MUX generates a combination of the latched tester data signal and the transformed tester data signal for transmission as an applied test data signal. The resulting applied test data signal has double the data rate of the tester data signal upon which it is based.

Testing of high speed DDR interface using single clock edge triggered tester data

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Fremont, CA, United States of America

Syed Khalid Azim