Cypress Semiconductor Corporation

Syed B Raza

Pradeep Kumar Bajpai

Hamid Khodabandehlou

Sumeet Gupta

Anup Nayak

Hagop A Nazarian

Jeffery Scott Hunt

Derwin W Mattos

Lin-Shih Liu

Stephen M Douglass

George M Ansel

Robert Glenn Rundell

Scott Allen Swindle

Godwin Gerald Arulappan

Nabil Masri

Michael L Lewis

Venkat Mandagulathur

Techniques for control of power switches in a USB Power Delivery (USB-PD) system are described herein. In an example embodiment, an integrated circuit comprises a programmable gate control circuit coupled to a provider field effect transistor (FET) and a consumer FET to provide control signals to the provider and consumer FETs in response to system conditions and application requirements of the USB-PD system. A pulldown current control circuit may provide additional control to slew rate for the slow turn-ON of provider and consumer FETs.

Programmable gate driver control in USB power delivery

Techniques for voltage discharge from a USB Power Delivery (USB-PD) VBUS line are described herein. In an example embodiment, an integrated circuit comprises a discharge control logic coupled to a first discharge circuit and to a second discharge circuit. The first discharge circuit configured to couple to a power source node on the VBUS line. The second discharge circuit configured to couple to an output node on the VBUS line. The discharge control logic is configured to independently control the first discharge circuit and the second discharge circuit to discharge the voltage on the VBUS line.

Programmable VBUS discharge in USB power delivery

A system comprising a memory controller coupled to a memory device is described. The memory device is coupled to, and is external to, the memory controller. The memory device includes a storage array having dual configurability to support both synchronous and asynchronous modes of operation.

Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain

A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U0) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

Re-enumeration of USB 3.0 compatible devices

A method of operating a memory interface circuit involves selectively operating the memory interface in either a synchronous mode or an asynchronous mode, the synchronous mode controlled by a first clock signal; in asynchronous mode, controlling an address latch for latching an address of a memory location in a memory array, the address latch controlled by an asynchronous address control signal synchronized to a second clock signal that is faster than a third clock signal used to operate the memory array.

Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock

A device can include a processor configured to write a first data structure to a memory, the first data structure comprising a list of at least one data channel; and a scheduler circuit comprising logic circuits responsive to the processor, the scheduler circuit configured to transfer data packets to the at least one data channel via a packet based serial data communication interface and according to the first data structure.

Host communication device and method with data transfer scheduler

Several embodiments including methods, systems, and physical computer-readable storage media are configured to multiplex a single end-point memory (EPM) structure between a HS USB interface and a SS USB interface, which includes determining whether the SS USB interface is enabled, if the SS USB interface is enabled, detecting the SS USB interface, selecting the HS USB interface, if the SS USB interface is enabled, but not detected, and multiplexing between a functionality of a HS USB device interface and a functionality of a HS USB host interface, if the SS USB interface is not enabled.

Methods, systems, and physical computer-readable media for multiplexing a single end-point memory structure between USB interfaces

A host device can download a firmware update to a peripheral device having previously enumerated with the host device. The host device can perform link training with the peripheral device in response to a re-enumeration indication received from the peripheral device. The link training can include switching a Link Training and Status State Machine (LTSSM) in the host device from an active state (U) to an RX.Detect state and synchronizing with the peripheral device in the RX.Detect state. The host device can re-enumerate with the peripheral device utilizing the firmware update after the host device completes link training with the peripheral device.

An embodiment of the present invention is directed to a system including a memory interface logic unit for receiving memory access requests and corresponding information, a processor coupled to the memory interface logic, a plurality of pre-fetch buffers for handling memory accesses coupled to the memory interface logic unit, an arbiter logic unit for pre-fetching data into the plurality of pre-fetch buffers, a memory device for storing data coupled to the arbiter logic unit and the plurality of pre-fetch buffers, and busy detection logic for informing the arbiter logic unit of the current operation of the processor. The arbiter logic unit facilitates memory access via pre-fetch buffers of the processor and the memory in different or independent clock domains. The arbiter logic further allows random access without introducing additional latency.

Arbitration method for programmable multiple clock domain bi-directional interface

An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory access device to reliably access memory in a time domain independent of a device issuing requests. The system may synchronize device resource information for requests made by a processor to access (e.g., read/write) locations of a memory device. The present invention synchronizes the device access information without restricting pulse width of a read/write signal or requiring a high speed clock.

Busy detection logic for asynchronous communication port

An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface circuit also includes logic, which enables the storage array to reside within substantially any clock domain.

A method includes receiving an endpoint address and corresponding endpoint data, the endpoint address identifying a logical endpoint associated with the endpoint data, storing the endpoint data to at least one of a plurality of memory buffers corresponding to the identified logical endpoint, and transmitting the endpoint data to a destination according to the endpoint address. A peripheral device includes a logical-to-physical memory map to store an endpoint address and corresponding endpoint data received from a first device, the endpoint address to identify at least one data stream capable of transferring the endpoint data to a second device, and a service unit to retrieve the endpoint address and corresponding endpoint data from the logical-to-physical memory map, and to transfer the endpoint data to the second device in the data stream identified by the endpoint address.

Implementation of logical endpoints in USB device

A controller circuit can provide communication paths between multiple host devices and at least one function interface (I/F), where a function I/F can allow access to a predetermined circuit function. The controller circuit can include an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a predetermined data transmission protocol and a data switching circuit coupled to the endpoint point buffer circuit. The data switching circuit is configurable to provide communication paths that enable a first host I/F and a second host I/F to access at least a same function I/F, and enable the first and second host I/Fs to communicate with one another.

Architectures for supporting communication and access between multiple host devices and one or more common functions

A controller circuit provides communication paths between multiple host devices and a target device. The controller circuit includes a first host idle detection circuit that determines when a first host interface (I/F) is in an idle state, an idle state being when the first host I/F is not communicating with the controller circuit. A switch circuit can selectively enables a controllable communication path between a second host I/F and a target device I/F. A first response circuit can be coupled to the first host I/F and output predetermined responses from the first host I/F in response to communications received on the first host I/F. The first response circuit outputting a predetermined response when at least the controller circuit has enabled the controllable communication path between a second host I/F and the target device I/F and disabled the controllable communication path between the first host I/F and the target device I/F.

Growing community of inventors

Sunnyvale, CA, United States of America

Syed B Raza