Waferscale Integration, Inc.

Syed Ali

Boaz Eitan

Reza Kazerounian

Yoram Cedar

An array of floating gate transistors is arranged so that in the transistors within the even numbered rows, the bit line on the left side of the transistor serves as the drain, and the bit line on the right side of the transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Conversely, in the odd numbered rows, the bit line on the right side of each transistor serves as the drain, the bit line on the left side of each transistor serves as the source, and the floating gate extends over the left side of the transistor channel. Thus, in order for the bit line decoder to determine which bit line is to be grounded and which bit line is to be connected to a sense amplifier, the bit line decoder also receives signals indicative of the row which has been addressed. In one embodiment, the array comprises redundant rows. The decoder is constructed so that any redundant rows can be used to replace either an odd or even-numbered row in the array. The array also includes a dummy transistor column. Means are provided for coupling a transistor from the dummy transistor column to the sense amplifier which has a floating gate on the same side of the channel as a transistor being read. Decode means are provided for coupling each dummy bit line to either ground or the sense amplifier.

Decoder for a floating gate memory

An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes a capacitive voltage divider for providing a first voltage proportional to the erase voltage, a reference voltage lead for providing a reference voltage and a control circuit for controlling the voltage multipler circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

On-chip high voltage generator and regulator in an integrated circuit

An EEPROM constructed in accordance with our invention includes a voltage multiplier for generating an erase voltage and a voltage regulator circuit for controlling the magnitude of the erase voltage. The voltage regulator circuit includes means for providing a first voltage proportional to the erase voltage, means for providing a reference voltage on a reference voltage lead, and means for controlling the voltage multiplier circuit so that if the first voltage is less than the reference voltage, the voltage multiplier circuit will increase the erase voltage, but if the first voltage is greater than the reference voltage, the voltage multiplier will not continue to increase the erase voltage. The voltage multiplier includes novel capacitors and transistors constructed using standard EEPROM processing to withstand high voltages without breaking down.

An EEPROM receives a first address from a microprocessor. If the first address equals a first predetermined value, the EEPROM goes into a programming mode. If the first address equals a second predetermined value, the EEPROM goes into an erase mode. The EEPROM interprets a second address received from the microprocessor as indicating the location where data is to be stored in the EEPROM. The EEPROM generates an internal write pulse which remains active until the EEPROM receives a subsequent write instruction from the microprocessor. In this way, it is not necessary to generate a wait instruction to the microprocessor to halt the microprocessor while the EEPROM is storing data. Also, it is not necessary to provide additional circuitry to control whether the EEPROM goes into the erase or programming modes.

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Cupertino, CA, United States of America

Syed Ali