Intel Corporation

Syed A Zaidi

Bharat N Zaveri

Nimish H Modi

Apparatus for detecting move instructions in which only registers are involved. The apparatus generates signals to disable the inclusion of any SIB byte, displacement bytes and immediate bytes from the instruction length when a move instruction which only requires processor registers is encountered. The apparatus uses the generated signals for instruction length calculation and instruction prefetch pointer generation.

Apparatus and method for modifying instruction length decoding in a

A microprocessor having an architecture for pipelining instructions to reduce the time necessary to execute sequential instructions including an arithmetic and logic unit for processing information; a register file for storing data to be used by the arithmetic and logic unit, the register file including individual registers from which data is read for operations by the arithmetic and logic unit and to which data is written which results from operations of the arithmetic and logic unit; and apparatus for obtaining updated data from a source other than the register file when sequential instructions processed by the arithmetic and logic unit change data in a particular register in the register file during a first instruction and then use the data in the register file which was changed in a second instruction so that the data in the particular register is stale at the time it is required for the second instruction.

Apparatus for register bypassing in a microprocessor

Apparatus for increasing the decoding speed of a microprocessor. The apparatus includes a first decoder for decoding macroinstructions. The first decoder includes apparatus for generating a single initial microinstruction vector from simple macroinstructions and from complex macroinstructions having a beginning microinstruction equivalent to a microinstruction for a simple macroinstruction. The first decoder also includes apparatus for indicating a beginning address for generating any remaining microinstruction vectors for a complex macroinstruction decoded by the first decoder. The apparatus for increasing the decoding speed of a microprocessor also includes apparatus, coupled to the first decoder, for generating any remaining microinstruction vectors for complex macroinstructions decoded by the first decoder. The apparatus for generating any remaining microinstruction vectors includes apparatus for responding to the apparatus for indicating a beginning address.

Method and apparatus for increasing the decoding speed of a

In a pipelined microprocessor which includes a prefetch unit for obtaining a plurality of instructions to be processed; a decode unit having a prefix state machine for decoding prefixes and determining their lengths, a decode circuit for decoding instructions and generating microcode vectors to be executed, and apparatus for counting the length of an instruction; and a microcontroller for sequencing microcode vectors; the improvement including apparatus for detecting the appearance of a particular prefixed instruction, apparatus responsive to the detection of the particular prefixed instruction for disabling the prefix state machine, apparatus in the decode circuit for decoding the particular prefixed instruction and causing the decode circuit to generate microcode vectors for the instruction, and apparatus for generating a request to the microcontroller to handle microcode vectors generated.

Method and apparatus for decoding conditional jump instructions in a

In a circuit for accomplishing arithmetic operations and including an ALU; a first register for holding a dividend to be divided and intermediate and final results of the operation; a second register for holding a divisor; and apparatus for sequentially causing the dividend to be shifted left by one bit and the divisor subtracted from or added to the highest order bits of the dividend and partial remainders to provide a result which determines a quotient bit and thereby practice the operation of non-restore division, the improvement including: apparatus for performing an XNOR operation on the result of any carryout from any addition or subtraction operation and the value of the highest order bit of the dividend or the partial remainder; and apparatus for providing the result of the XNOR operation as the quotient bit to the arithmetic and logic unit.

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Santa Clara, CA, United States of America

Syed A Zaidi