Texas Instruments Corporation

Sydney W Poland

Karl M Guttag

Robert J Gove

Christopher Jensen Read

Keith Balmer

Jeremiah E Golston

Nicholas K Ing-Simmons

Philip John Moyse

Phillip Moyse

Jerry R Van Aken

Michael C Gill

Erick D Oakland

Nicholas Ing Simmons

A data processing apparatus iteratively forms quotient, includes data registers (,) for storing various initial and intermediate quantities, a multiplexer (,) for selecting data from one of two data registers, a barrel rotator (,) and an arithmetic logic unit (,). A first register (,) stores the numerator, which is left shifted each iteration. A second register (,) stores the difference formed by the prior trial subtractions. A status register (,) set by the prior arithmetic logic unit (,) result controls the selection made by the multiplexer (,). A barrel rotator (,) rotates the data selected by multiplexer (,). The arithmetic logic unit (,) subtracts the divisor from the rotated quantity this result controls the iterative division process. If the difference is less than zero, then the rotated data is selected and the quotient bit is &ldquo;0&rdquo;. Otherwise, the prior difference is selected and the quotient bit is &ldquo;1&rdquo;. In the preferred embodiment, the numerator is split between two registers. The trial difference involves only the most significant bits of the numerator. In the preferred embodiment, the inverse of the divisor is stored and the difference is formed by adding the inverse of the divisor. The division processing repeats until the quotient is completely formed and loop logic controls the number of iterations. Also, the data processing apparatus is embodied as at least one digital image/graphics processor (,) as a part of a multiprocessor (,) formed in a single integrated circuit.

Division by iteration employing subtraction and conditional source selection of a prior difference or a left shifted remainder

A data processing apparatus includes plural data registers, an arithmetic logic unit and a status register. The status register stores a plurality of different types of status bits. These status bits could be a negative status bit, a carry status bit, an overflow status bit and a zero status bit. These status bits are normally set dependent upon the condition of the result generated by the current arithmetic logic unit operation. A status bit protect instruction type permits selection of status bits protected from modification corresponding to the current arithmetic logic unit result. This status bit protect instruction preferably includes individual protect bit corresponding to each status bit. If a protect bit has a first digital state, then the corresponding status bit may be modified corresponding to the current arithmetic logic unit result. If the protect bit has a second opposite digital state, then the corresponding status bit is protected from modification according to the arithmetic logic unit results.

Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of '1'. This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Three input arithmetic logic unit with barrel rotator

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of '1'. This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Three input arithmetic logic unit with shifter

A memory store operation comes from one of a pair of registers selected by an arithmetic logic unit condition. An instruction logic circuit (250, 660) controls an addressing circuit (120) to store data in a first register into memory if a selected status bit has a first state and to store data in a second register associated with the first register into memory if the selected status bit has a second state in response to a register pair conditional store instruction. The bits may indicate a negative output of the arithmetic logic unit (230), a carry out signal, an overflow, or a zero output. The register pair conditional store instruction designates a particular one of the status bits to control the conditional store. The instruction logic circuit (250, 660) substitutes the selected status bit for a least significant bit of the register number. Thus memory store is from the first register if the status bit is '1' and is from the second register if the status bit is '0'. In a further embodiment the register pair conditional write instruction is conditional. The write operation aborts if the designated condition is true. In the preferred embodiment of this invention, the arithmetic logic unit (230), the status register (210), the data registers (200) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71) as a part of a multiprocessor formed in a single integrated circuit (100) used in image processing.

Memory store from a register pair conditional upon a selected status bit

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of '1'. This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Three input arithmetic logic unit capable of performing all possible

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of '1'. This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Three input arithmetic logic unit with shifter and/or mask generator

A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of '1'. This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.

Three input arithmetic logic unit with shifter and mask generator

A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of '1'. This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.

Three input arithmetic logic unit with barrel rotator and mask generator

A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.

Base address generation in a multi-processing system having plural

Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation. An arithmetic logic unit operation generates a status bit loaded into a status register or is split into sections and generates a status bit for each section stored in a multiple flags register (211) used to load the loop. count register. If this is zero then the loop priority logic reloads the program counter (701) with the loop start address and repeats the loop. If this is nonzero, program counter (701) may increment normally or will be loaded with the loop start address of a higher priority loop.

Hardware branching employing loop control registers loaded according to

Memory store from a selected one of a register pair conditional upon the

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of '1'. This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.

Three input arithmetic logic unit with shifting means at one input

A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.

Data processor having capability to perform both floating point

This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to '0'. Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is '1'. If the difference is less than zero, then the next quotient bit is '0'. The difference is substituted for the N most significant bits of the numerator, if this difference was greater than or equal to zero. Then the numerator is left shifted one place. These iterations repeat until the number of iterations exceeds N. Then the quotient is completely formed and the data of the last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are '0'. Using pre- and post-processing this technique can be used with signed numbers. In the preferred embodiment of this invention, the division logic is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing.

Growing community of inventors

Katy, TX, United States of America

Sydney W Poland