Motorola Corporation

Other

Syd R Wilson

Charles J Varker

Thomas Allen Wetteroth

Richard B Gregory

Gordon M Grivna

Charles E Weitzel

Karen Elizabeth Moore

Clarence J Tracy

Mohit Bhatnagar

John L Freeman, Jr

Robert J Mattox

Robert L Duffin

Hank Hukyoo Shin

Jeffrey Pearse

Richard W Gurtler

Orin W Holland

Schyi-Yi Wu

Wayne M Paulson

Yee-Chaung See

Thomas E Zirkle

William E Gandy, Jr

Han-Bin K Liang

James A Sellers

Darrell Keith Thomas

Stella Q Hong

Paul R Proctor

Arthur T Lowe

Marie E Burnham

Tommie R Huffman

Jerry L Chruma

Richard L Peterson

Robert P Lorigan

Systems and methods are described for transfer of a thin-film via implantation, wafer bonding, and separation. A method for transfer of a thin-film, includes: implanting a source crystal with ions along a crystallographic channel and at a temperature of at least approximately 200&deg; C. to i) form a strained region and ii) define the thin-film; then bonding a surface of the thin-film to a target wafer; and then separating a) the target wafer and the thin-film from b) a remainder of the source crystal along the strained region. The systems and methods provide advantages because the electrical carriers in the crystal, and consequently the thin-film, are not deactivated and the quality of the transferred thin-film is improved.

Method for transfer of thin-film of silicon carbide via implantation and wafer bonding

A silicon carbide transistor (,) is formed from a silicon carbide film (,) that is formed on a silicon carbide substrate bulk (,). A conductor pattern layer (,) is formed on the silicon carbide film (,) and the silicon carbide film (,) removed from the silicon carbide substrate bulk (,) and attached to a substrate (,) of a dissimilar semiconductor material.

Silicon carbide transistor and method therefor

A method of fabricating a semiconductor device on thinned wide bandgap material including providing a support having a planar surface and a semiconductor substrate. Implanting a layer of ions in the substrate to create a layer of microbubbles defining a thin film having a planar surface and a remaining mass separated by the layer of implanted ions. Intimately contacting the planar surface of the thin film to the planar surface of the support and heating the support and substrate to separate the remaining mass from the thin film. A semiconductor device is formed on the thin film, and the support is thinned.

Method of fabricating a semiconductor device with a thinned substrate

A semiconductor structure (20) includes a silicon layer (16) formed on an oxide layer (14). Gettering sinks (31, 32) are formed in the silicon layer (16). Lateral gettering is performed to effectively remove impurities from a first section (26) of the semiconductor layer (16). An insulated gate semiconductor device (40) is then formed in semiconductor layer (16), wherein a channel region (55) of the device (40) is formed in the first section (26) of the semiconductor layer (16). A gate dielectric layer (42) of the device (40) is formed over a portion of the first section (26) after the lateral gettering process, thereby enhancing the integrity of the gate dielectric layer (42).

Method for fabricating a semiconductor device using lateral gettering

A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.

Structure and method for metallization of semiconductor devices

An integrated circuit substrate (26) is formed with active circuit elements (24, 32) on first and second surfaces of the substrate. The active circuit elements are interconnected with though-substrate vias (28) to minimize signal routing and reduce propagation delay. The through-substrate vias may be formed with a plurality of holes (52) through the IC substrate. A dielectric layer (54) is deposited on the surface of the IC substrate and through the holes. A conductive layer (56) is deposited through the holes to form the through-substrate vias. The dielectric layer is removed from the surface of the IC substrate to leave the through-substrate vias isolated from the IC substrate by the dielectric layer. A second substrate (26) is formed as described and the two substrates are joined as a two-sided chip (21) with active circuit elements on both sides interconnected by through-substrate vias.

Method of forming vias through two-sided substrate

A method of fabricating a semiconductor structure includes providing a substrate having at least one layer formed thereon. At least two trenches are formed through the layer and into the substrate wherein at least one trench is for isolation and at least one trench is for making contact to the substrate. After a trench liner is formed on the sidewalls of the trenches, the trenches are filled with doped semiconductor material. The doped semiconductor material in the trench for isolation is then anodized. After the anodization, the anodized trench fill material is oxidized.

Method of forming substrate contact trenches and isolation trenches

A method of fabricating a trench structure includes providing a substrate having a first layer disposed on a surface thereof and a second layer disposed on the first layer. A trench is formed through the first and second layers and into the substrate. A dielectric liner is formed on the sidewalls of the trench which is then filled with a trench fill material. Portions of the trench liner disposed above the trench fill material are removed and a conformal layer is then formed on the trench structure. The conformal layer and a portion of the trench fill material are then oxidized.

Method of fabricating a trench structure

A method for forming a via contact for devices having multilayer metallization is provided wherein a sacrificial layer is formed over a bottom interconnect layer, and an interlayer dielectric is formed on the sacrificial layer. A via is etched in the interlayer dielectric, exposing the sacrificial layer. The sacrificial layer is isotropically etched to expose an area of the interconnect metal that is larger than the area of the via and a via metallization is selectively formed on the interconnect metal by chemical vapor deposition so that the via, including a void created by the isotropic etch of the sacrificial layer, is filled with the via metallization, thereby providing a contact area to the bottom interconnect metal which is larger than the via metallization itself.

Process for making a multilayer metallization structure

A method for determining silicon mass 28 beam purity prior to implanting gallium arsenide by implanting silicon in a silicon monitor wafer and analyzing the damage created by the implantation.

Method for determining silicon (mass 28) beam purity prior to

A means and method is described for shielding semiconductor charge storage devices from the effects of particles or ionizing radiation absorbed within the bulk of the semiconductor substrate, by providing a free carrier shield consisting of a buried layer of very low lifetime in the undisturbed material below the depletion regions associated with the charge storage devices. The very low lifetime layer is obtained by ion implantation of a super-saturated zone of impurities such as oxygen which provide deep recombination centers and which react chemically with the substrate material so as to provide thermally stable complexes which do not anneal away during post implant heating cycles. Concentrations of lifetime killing impurities significantly exceeding the solid solubility limit are achieved so that the lifetime reduction in the carrier shield region greatly exceeds that obtainable by prior art methods. Partial shielding is also provided against carriers injected by nearby junctions or introduced by charge pumping during circuit operation.

Charge storage depletion region discharge protection

Implantation of oxygen or nitrogen in polysilicon layers to a dose above about 10.sup.15 ions/cm.sup.2 retards rapid grain boundary migration of conventional dopants such as B, P, As, Sb, and the like during dopant activation. Pre-annealing of the poly films to increase the grain size also decreases rapid grain boundary migration. The effects can be combined by first pre-annealing and then implanting oxygen or nitrogen before introducing the dopant. It is desirable to anneal the oxygen implant before introducing the dopant to allow for oxygen diffusion to the grain surfaces where it precipitates and blocks the grain boundaries. Vertical and lateral migration of the dopants can be inhibited by placing the implanted oxygen or nitrogen between the dopant and the location desired to be kept comparatively free of dopants. When very high dopant activation temperatures are used the blocking effect of the oxygen on the grain boundaries is overwhelmed by dopant diffusion through the grains.

Means for stabilizing polycrystalline semiconductor layers

Hillock formation as a result of heating uncapped polycrystalline silicon layers can be avoided by first implanting the uncapped poly layers with silicon, oxygen, or nitrogen prior to heating. Equivalent mono-atomic oxygen or nitrogen doses in the range of about 10.sup.15 to about 5.times.10.sup.16 ions/cm.sup.2 at energies in the range 10-50 keV are useful with good results being obtained with equivalent oxygen doses of 2.times.10.sup.15 ions/cm.sup.2 at 30 keV. When polysilicon layers with this oxygen implant are heated to about 1150 degrees C., a temperature which would ordinarily produce pronounced hillock formation in un-capped, un-treated poly layers, it is found that hillock formation is suppressed. The implanted oxygen concentrations are far below what is required to produce a separate oxide layer or phase. Some effect on poly layer sheet resistance is observed for implanted oxygen but the implanted layers have sheet resistances within a factor of two of those without the oxygen implants.

Method of preventing hillock formation in polysilicon layer by oxygen

Zener diodes and other semiconductor junctions having very low noise characteristics and improved yield may be obtained by first ion implanting a suitable impurity into a substrate wafer, and then forming the p-n junction using a very rapid thermal activation and annealing process. For p-n junctions formed with boron (.sup.11 B) implanted into n-type silicon to a peak concentration exceeding 10.sup.20 atoms/cm.sup.3, the rapid activation process comprises heating from about room temperature to about 1150.degree. C. in 12-30 seconds, and then cooling back below 1000 degrees C. in less than 5 seconds. Noise voltages measured on devices formed using the invented process were typically much lower and more narrowly grouped than on devices of the prior art. Dynamic impedance was also slightly reduced.

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Phoenix, AZ, United States of America

Syd R Wilson