Wafertech, Inc.

Swen Wang

A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions.

Nonvolatile memory cell with improved isolation structures

An array of floating gate transistors of a non-volatile memory, NVM, cell includes floating gate transistors separated from one another by high-concentration dopant impurity regions and without using shallow trench isolation (STI) or field oxide (FOX) isolation structures. The array is formed over a substrate portion that includes a continuous and planar upper surface. The high-concentration dopant impurity regions are formed in a P-field region and are formed of the same dopant impurity species as the P-field region but of a higher concentration. The floating gate transistors are split-gate floating gate transistors in some embodiments.

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Camas, WA, United States of America

Swen Wang