Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

Swee Tuck Woo

Sung Mun Jung

Sanford Chu

Jianbo Yang

Kian Hong Lim

Liang Choo Hsia

Xiaoyu Chen

Donghua Liu

Siow Lee Chwa

Rachel Low

Louis Lim

Ching Dong Wang

Louis Yoke Leng Lim

A method of forming a device is disclosed. The method includes providing a substrate and forming a device layer on the substrate having a formed thickness T. A capping layer is formed on the substrate having a formed thickness T. Forming the capping layer consumes a desired amount of the device layer to cause the thickness of the device layer to be about the target thickness T. The thickness of the capping layer is adjusted from Tto about a target thickness T.

Dielectric stack

A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area and forming first and second gates of first and second transistors in the cell area. The first gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the first gate are separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. The method also includes forming first and second junctions of the first and second transistors. A first gate terminal is formed and coupled to the second sub-gate of the first transistor. A second gate terminal is formed and coupled to at least the first sub-gate of the second transistor.

EEPROM cell

A method of forming a device is disclosed. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second gates of first and second transistors in the cell area are formed. The first gate includes first and second sub-gates separated by a first intergate dielectric layer. The second gate includes a second sub-gate surrounding a first sub-gate. The first and second sub-gates of the second gate are separated by a second intergate dielectric layer. First and second junctions of the first and second transistors are formed. The method also includes forming a first gate terminal coupled to the second sub-gate of the first transistor and a second gate terminal coupled to at least the first sub-gate of the second transistor.

A non-volatile memory cell includes an access and a storage transistor coupled in series. The memory cell is formed on a thin gate well tailored for transistors with thin gate dielectrics. The access transistor is a hybrid transistor which includes a gate with a thick gate dielectric layer formed on the thin gate well.

Non-volatile memory cell with a hybrid access transistor

An integrated circuit memory system including a substrate formed with equidistant spaced shallow trench isolation regions. Forming active regions and dummy active regions within the substrate between the equidistant spaced shallow trench isolation regions. Forming sources and drains within the active regions. Providing wordlines and source lines extending in a first direction and bitlines extending in a second direction. Forming contact regions over the dummy active regions for strapping the wordlines and the source lines to the bitlines.

Growing community of inventors

Singapore, Singapore

Swee Tuck Woo