Intel Corporation

Swee Boon Tan

Keng L Wong

In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input, a second control input, and a third control input, wherein the first control input, the second control input, and the third control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the first charge pump, the second charge pump, and the first bias generator. A third bias generator is coupled to the third control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

Self-biased phased-locked loop

In general, in one aspect, the disclosure describes a phase-locked loop circuit. The circuit includes an oscillator having a first control input and a second control input, wherein the first control input and the second control input act to control output frequency of the oscillator. The circuit further includes a first charge pump and a second charge pump. A first bias generator is coupled to the first control input of the oscillator and can receive electrical input from the first charge pump and the second charge pump. A second bias generator is coupled to the second control input of the oscillator and can receive electrical input from the second charge pump and the first bias generator.

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Penang, Malaysia

Swee Boon Tan