Marvell International Limited

Swee-Ann Teo

Yonghua Song

Lawrence Tse

King Chun Tsai

Sang Won Son

A voltage regulator for a plurality of radio frequency subcircuits of a radio frequency circuit. A first transistor configured to receive, based on a comparison between a reference voltage signal and a feedback signal, a bias signal corresponding to a desired regulated voltage for the plurality of radio frequency subcircuits, output the bias signal, and generate the feedback signal according to the bias signal as output from the first transistor. A second transistor configured to receive the bias signal as output from the first transistor and provide, based on the bias signal, the desired regulated voltage to a respective first one of the plurality of radio frequency subcircuits. A third transistor is configured to receive the bias signal as output from the first transistor and provide, based on the bias signal, the desired regulated voltage to a respective second one of the plurality of radio frequency subcircuits.

Voltage regulator for providing a regulated voltage to subcircuits of an RF frequency circuit

A radio frequency transceiver for a wireless communications device transceiver comprising a plurality of subcircuits, a first regulator circuit, and a plurality of second regulator circuits. Each subcircuit is configured to perform an operation of the radio frequency transceiver in accordance with a corresponding regulated voltage. A first regulator circuit is configured to provide a bias signal based on a reference signal and a feedback signal indicative of the bias signal. The bias signal corresponds to a desired regulated voltage for the plurality of subcircuits. A plurality of second regulator circuits corresponding to respective ones of the plurality of subcircuits are each configured to provide the regulated voltage to the respective one of the plurality of subcircuits.

Voltage regulator for high performance RF systems

A voltage regulator for a radio frequency circuit including a master regulator circuit, a first slave regulator circuit, and a first radio frequency subcircuit. The master regulator circuit is configured to i) receive a reference voltage signal and a feedback signal and ii) output a control voltage signal based on the reference voltage signal and the feedback signal. The first slave regulator circuit is configured to i) receive the control voltage signal and ii) output a first regulated supply voltage signal based on the control voltage signal. The first radio frequency subcircuit is configured to receive the first regulated supply voltage signal. The control voltage signal corresponds to a desired supply voltage for the first radio frequency subcircuit.

A sigma delta modulated phase lock loop reduces quantization noise by using phase interpolation to increase an effective frequency resolution of the dividing ratio of a divider.

Sigma delta modulated phase lock loop with phase interpolation

A voltage regulator comprises a master regulator circuit that receives a reference signal and that generates a feedback signal and a master bias signal. The master bias signal is based on the reference signal and the feedback signal. N slave regulator circuits receive the master bias signal from the master regulator circuit and output N regulated output signals to N circuits, respectively, where N is an integer greater than one.

Apparatus, systems, and methods implementing techniques for converting clock signals are described. A voltage-based input clock signal is received and converted into a current-based clock signal. An electrical current of the current-based clock signal is varied in response to the input clock signal while a voltage of the current-based clock signal remains substantially constant.

Clock signal conversion system

Apparatus, systems, and methods implementing techniques for filtering signals are described. A filter circuit receives an input signal and produces a corresponding filtered signal. The filter circuit has a transfer function that relates the filtered signal to the input signal. The transfer function includes at least one pole and at least one zero, where at least one of the zeros corresponds to a first frequency, and at least one of the poles corresponds to a second frequency. The apparatus also includes a negative-transconductance circuit that is coupled to the filter circuit and that increases a magnitude of a component of the filtered signal that corresponds to the second frequency.

Filter circuit with negative transconductance

A voltage-controlled oscillator (VCO) circuit includes first, second, third, and fourth transistors, wherein said third and fourth transistors bias the second and first transistors, respectively. First and second capacitances communicate with the first, second, third, and fourth transistors. A first input receives a first capacitance adjustment signal. At least one second input receives a second capacitance adjustment signal. The first capacitance has a first end connected to he first input and the third transistor. The second capacitance has a first end connected to the second input and the fourth transistor.

Self-biased active VCO level shifter

A charge pump includes first and second pairs of differential transistors. Each transistor includes control, first, and second terminals. First and second charge pump drivers communicate with the control terminal of one of the first pair of differential transistors and one of the second pair of differential transistors, respectively. Third and fourth charge pump drivers communicate with the control terminal of the other of the first pair of differential transistors and the other of the second pair of differential transistors, respectively. The first through fourth charge pump drivers include respective pairs of differential transistors that receive control signals from respective control circuits.

Bootstrapped charge pump driver in a phase-lock loop

A voltage-controlled oscillator (VCO) circuit includes first, second, third, and fourth transistors, each with a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor communicates with the first terminal of the second transistor. The control terminals of the third and fourth transistors communicate with the second terminals of the first and second transistors, respectively. The first terminals of the third and fourth transistors communicate with the control terminals of the first and second transistors, respectively. First ends of first and second capacitances communicate with the second terminals of the first and second transistors, respectively. Second ends of the first and second capacitances communicate with the control terminals of the first and second transistors, respectively.

A voltage regulator includes a master regulator circuit that receives a reference signal, that generates a master bias signal and that includes a transistor having a first gain. A first slave regulator circuit includes a first transistor having a second gain that is substantially equal to unity gain, a control terminal that receives the master bias signal from the master regulator circuit, a first terminal and a second terminal that outputs a first regulated output signal. A second slave regulator circuit includes a second transistor having a second gain that is substantially equal to unity gain, a control terminal that receives the master bias signal from the master regulator circuit, a first terminal, and a second terminal that outputs a second regulated output signal.

A differential circuit comprises first, second, third and fourth devices that have first, second, third and fourth control terminals, respectively. The second and fourth devices are arranged in series with the first and third devices, respectively. A first output communicates with the first device and the second device. A second output communicates with the third device and the fourth device. First and second inputs communicate with the first and fourth control terminals, respectively. The first, second, third and fourth devices are the same type of devices. The third and second control terminals follow the first and fourth control terminals. When the first device pushes, the third device pulls. When the first device pulls, the third device pushes. When the fourth device pushes, the second device pulls. When the fourth device pulls, the second device pushes. The second and third devices and the first and fourth devices are matched.

Push-pull buffer/amplifier

A differential circuit includes first, second, third, and fourth transistors each having a control terminal, a first terminal and a second terminal. A first input terminal communicates with the control terminals of the second and third transistors. A second input terminal communicates with the control terminals of the first and fourth transistors. A first output terminal communicates with the second terminal of the second transistor and the first terminal of the fourth transistor. A second output terminal communicates with the second terminal of the first transistor and the first terminal of the third transistor. The first input terminal communicates with the control terminals of the second and third transistors through first and second capacitances, respectively. The second input terminal communicates with the control terminals of the first and fourth transistors through third and fourth capacitances, respectively. A capacitance communicates with the second terminals of the third and fourth transistors.

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Swee-Ann Teo