University of Florida Research Foundation Inc

Case Western Reserve University

Intel Corporation

The Cleveland Clinic Foundation

The United States Government as Represented by the Department of Veterans Affairs

Brookhaven Science Associates, Lcc

Swarup Bhunia

Prabuddha Chakraborty

Abdulrahman Alaql

Patanjali Sristi Lakshmiprasanna Sriramakumara

Christopher Vega

Soumyajit Mandal

Jonathan William Cruz

Reiner Dizon

Md Moshiur Rahman

Sandip Ray

Shubhra Deb Paul

Aritra Dasgupta

Naren Vikram Raj Masna

Tamzidul Hoque

Rohan Reddy Kalavakonda

Pravin Dasharth Gaikwad

Roozbeh Tabrizian

Nij Dorairaj

Margot S Damaser

Steve Majerus

Hui Zhu

David Kehlet

Dennis Bourbeau

Parker Difuntorum

Fengchao Zhang

Atul Prasad Deb Nath

Naren Masna

Robert Karam

Abhishek Anil Nair

Robert Parker

Mark M Tehranipoor

Shuo Wang

Domenic J Forte

Prabhat Kumar Mishra

Navid Asadizanjani

Haoting Shen

Mason Greer

Toan Trung Nguyen

Cheng Chen

Philip X -l Feng

Rajat Subhra Chakraborty

Seetharam Narasimhan

David Joseph Ariando

Greg M Stitt

Kai Yang

Saranyu Chattopadhyay

Robert A Karam

Aritra Bhattacharyay

Sudipta Paria

Kshitij Raj

Joel B Harley

Anamika Bhuniaroy

Junjun Huan

Abhishek Basak

Yu Zheng

Lili Du

Ting He

Various embodiments of the present disclosure provide electromagnetic based secure contact-less integrity verification for an integrated circuit. In one example, an embodiment provides for mapping a signal to a pseudo-random number generator (PRNG) seed value, generating a PRNG output digital signal based on the PRNG seed value, encrypting the PRNG output digital signal based on a cipher function and a key, and generating an electromagnetic signal associated with the PRNG output digital signal to facilitate non-contact sensing of the electromagnetic signal by a probing system.

Electromagnetic based secure contact-less integrity verification of hardware and/or software for integrated circuits

A method and system are directed to protecting hardware IP, particularly of ASIC designs. Programmability is introduced into an ASIC design to increase the difficulty of formulating ASIC designs as Boolean Satisfiability (SAT) problems. Fine-grain redaction of security-critical information from a design is employed by removing high-entropy logic blocks and subsequently inserting programmable components in place of the redacted portion to hide the actual design intent.

Programmable application-specific array for protecting confidentiality and integrity of hardware IPS

A mask apparatus that is configured to prevent airborne pathogens from reaching an individual by actively mitigating airborne droplets that have a pathogen. In one example, the mask apparatus comprises a sensor device, a mitigator device, and a controller. The sensor device comprises an aerosol detector that is configured to perform a light measurement of an airborne aerosol droplet in an area proximate to the wearable apparatus. The mitigator device is configured to initiate a mitigation action directed at the airborne aerosol droplet. The controller is data communication with the sensor device and the mitigator device. The controller is configured to determine that the airborne aerosol droplet has a pathogen based at least in part on the light measurement captured by the sensor device and cause the mitigator device to initiate the mitigation action based on the airborne aerosol droplet having the pathogen.

System and method for closed-loop active sensing and protection against airborne pathogens

The present disclosure describes various embodiments of systems, apparatuses, and methods of protecting an integrated circuit. One such method comprises operating the integrated circuit under a normal mode of operation; detecting, by a decommission controller, a triggering condition for a decommission operation to be initiated for the integrated circuit; initiating, by the decommission controller, a decommission mode for the integrated circuit after detection of the triggering condition; and causing, by the decommission controller, functionality of the integrated circuit to be irreversibly disabled after initiating the decommission mode. Other methods, systems, and apparatus are also presented.

Decommissioning and erasing entropy in microelectronic systems

A reconfigurable JTAG includes, in part, a core logic, a boundary scan chain cell, one or more reconfigurable blocks (RBs), and a reconfigurable block (RB) programming module. The RBs may include, in part, one or more reconfigurable boundary scan chain blocks (RBB) adapted to couple the boundary scan chain cell to the core logic and to input/output (I/O) ports of the reconfigurable JTAG. The RBs may also include, in part, one or more additional reconfigurable logic (ARL) blocks to provide enhanced logic for locking operations. The RB programmable module may communicate with a memory storing data for configuring the RBBs and ARLs. The RB programming module may configure the RBBs and ARLs based at least in part on the data stored in the memory to disable access to the I/O ports of the JTAG. The RB programming module may configure the RBBs to encrypt the I/O ports in accordance with a cipher algorithm. The RB programming module may also configure the RBBs and ARLs to compare a counter's count to a predefined time and lock the I/O ports after an expiration of the predefined time.

Reconfigurable JTAG architecture for implementation of programmable hardware security features in digital designs

In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for altering a design of a hardware intellectual property (IP). In accordance with various embodiments, a representation of the design of the hardware IP is converted to generate a control and data flow graph (CDFG) for the design. An entropy analysis of the CDFG is conducted to identify one or more control paths and/or data paths for removal. Responsive to identifying control path(s) for removal, control logic for the control path(s) is removed from the design and replaced with first reconfigurable logic. Responsive to identifying data path(s) for removal, datapath logic for the data path(s) is removed from the design and replaced with second reconfigurable logic. Logic synthesis is then performed on the design, along with verification to check functional correctness of the design of the hardware.

Removal of hardware intellectual property and programmable replacement

A joint compression and encryption system is configured to retrieve, from a local memory or image capture device, an image file including a first plurality of segments. The system is further configured to identify, for one or more segment of the first plurality of segments, a matching segment in a local segmentation repository. The system is further configured to compress remaining segments of the first plurality of segments for which no matching segment was identified into a compressed remaining segment set. The system is further configured to transmit, via an unsecure communication channel and to a second computing entity, the identifications of the matching segments, and the compressed remaining segment set. The system is further configured to, prior to retrieving the image file, perform a handshake or calibration process. The system is further configured to encrypt the matching segments using a key into an encrypted segment set and transmit the key to the second computing entity. In embodiments, the second computing entity, using the key, decrypts the encrypted segment set.

Predictive joint compression and encryption for images and videos

Apparatus, systems, and methods described herein relate generally to on-the-go entity-to-entity charging for multi-level battery-powered entities in transportation systems. A method can include determining charge levels, current positions, battery configuration, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a nearby EV for on-the-go peer-to-peer charging. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and one or more other EVs that have excess charge to transfer, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between EVs and/or a charging entity. A heuristic battery architecture compiler can be used to optimize battery architecture.

Multi-level battery systems for battery-operated entities, methods for rapid charge transfer therebetween, and methods for optimizing entity routing and network charge distribution

Disclosed are various embodiments related to coordinated monitoring and responding to an emergency situation at a building structure as a supplement to a traditional emergency response. In some embodiments, a system comprises a computing device that is configured to receive sensor data from a sensor network. The sensor network includes monitoring units that monitor various locations of an infrastructure. The computing device determines an occurrence of an emergency event at a location in the infrastructure using an anomaly detector model based at least in part on the sensor data. A hybrid mobile unit is instructed by the computing device to navigate to the location of the emergency event. The hybrid mobile unit is configured to provide mobile sensor data associated with the location to confirm the emergency event.

Smart infrastructures and first-responder network for security and safety hazards

In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, and computing entities for modifying a design of a hardware IP. According to one embodiment, a method is provided, the method including generating a control and data flow graph (CDFG) representation for portions of the design. The method further includes partitioning the CDFG representation into a set of partitioned sub-graphs. The method further includes, for each partitioned sub-graph, generating a merged sub-graph to form a set of merged sub-graphs. Generating the merged sub-graph for each partitioned sub-graph involves generating a container sub-graph and merging the container sub-graph with the partitioned sub-graph to form the merged sub-graph. The container sub-graph may be a modification of the partitioned sub-graph with respect to an identified feature, in some examples. The method further includes synthesizing a modified design of the hardware IP including the set of merged sub-graphs.

Steganography of hardware intellectual property

The present disclosure describes various embodiments of systems, apparatuses, and methods for drone-based administration of remotely located devices. One such method comprises deploying an unmanned aerial vehicle from a base station, wherein the base station assigns a maintenance order to the unmanned aerial vehicle for servicing of a remote device, traveling, by the unmanned aerial vehicle, to the location of the remote device, authenticating, by the unmanned aerial vehicle, a valid identification of the remote device; upon the remote device being authenticated by the unmanned aerial vehicle, servicing the remote device by at least charging a power supply of the remote device and transferring contents of a device log to the unmanned aerial vehicle; and after completing the servicing of the remote device; returning to the base station and transferring contents of the device log to the base station.

Drone-based administration of remotely located instruments and gadgets

The present disclosure describes systems, apparatuses, and methods for obfuscation-based intellectual property (IP) watermark labeling. One such method comprises identifying, by one or more computing processors, a specific net within an integrated circuit design that is likely to be used in a malicious attack; and adding additional nets to the integrated circuit design that add additional logic states to a finite state machine present in the integrated circuit design. The additional logic states comprise watermarking states for performing authentication of the integrated circuit design, in which a watermark digest can be captured upon application of secret key inputs to the additional nets. Other methods, systems, and apparatuses are also presented.

Framework for obfuscation based watermarking

Various embodiments of the present disclosure provide a scan-based architecture for register-transfer-level (RTL) or gate-level designs that improves the security of scan chain-based design-for-testability (DFT) structures. In various embodiments, the scan-based architecture includes invisible scan chains that are hidden in such a way that an attacker cannot easily identify or locate the invisible scan chains for exploitation and revealing internal secure information of the design. The invisible scan chains are dynamically configurable into a scan chain with select flip-flops, such that scan paths of the invisible scan chains may be different between different designs, chips, or testing operations. Various embodiments further employ key-based obfuscation by combining a scan control finite state machine with existing state machines within a design, which improves design security against unauthorized use and increases confidentiality. Specific sequences of key patterns cause the design to transition into a test mode or a normal mode.

Invisible scan architecture for secure testing of digital designs

A system for secure testing and provisioning of an integrated circuit (IC) includes, in part, a secure reconfigurable key provisioning architecture (SLEEVE) module disposed in the IC, and a secure asset provisioning hardware entity (SAPHE) module. The IC may include, in part, a modified IEEE 1500 wrapper to control its operation modes. The SLEEVE module may include, in part, an encoding/decoding module and an unlocking module. The encoding/decoding module may include, in part, a decode key stream cipher module, an encode key stream cipher module, Seed Key programmable linear-feedback shift registers (LFSRs), Initialization Vector (IV) LFSRs, and configuration registers. The encoding/decoding module may be configured to generate key bits for decoding and encoding inputs and outputs of the IC. The unlocking module may include, in part, a pattern matching block and a counter. The unlocking module may be configured to enable write access to the configuration registers. The SAPHE module may include, in part, a microcontroller, a logging module, a provisioning module, and a communications module. The SAPHE module may be configured to interact with the IC to obtain a status of the IC during a testing and provisioning process. The logging module may include, in part, dedicated memory segments to store values for configuring the SLEEVE module and unlocking patterns for enabling write access to the configuration registers. The provisioning module may include, in part, a content accessible memory (CAM) module to store encrypted test patterns and encoded asset provisioning vectors for intellectual property (IP) blocks in the IC.

Establishing trust in untrusted IC testing and provisioning environment

Apparatus, systems, and methods described herein relate generally to autonomous mobile units carrying a modular configurable battery system that may attach and power mobile units in transportation systems. A method can include determining charge levels, current positions, and transport speeds for an electric vehicle (EV), identifying one or more EVs in need of charging, and mobilizing a Mobile Charging Station (MoCS) to deliver one or more external batteries. A processor, with a memory including computer program code, can be configured to receive current charge level data for mobile battery-powered entities, identify one or more EVs to be charged and the proximity of both MoCS and physical battery stations, and send charging instructions to the EVs. A routing and charge transaction scheduling algorithm can be used to optimize the route of one or more battery-powered entities and to schedule charge transactions between the EV and MoCS and/or the battery station.

System and method for a battery on wheels (BoW) for charging mobile battery-operated units

Growing community of inventors

Gainesville, FL, United States of America

Swarup Bhunia