Qualcomm Incorporated

Intel Corporation

Swaraj Sha

Kunal Mukesh Desai

Dharmesh Parikh

Vikrant Kumar

Saurabh Jaiswal

Sreenivas Subramoney

Stanislav Shwartsman

Lihu Rappoport

Pavel I Kryukov

An apparatus includes memory circuitry including a first data structure and prefetch circuitry that is coupled to the memory circuitry. The prefetch circuitry is to store, in the first data structure, a first subregion entry corresponding to a first subregion of a memory region allocated to a program. The first subregion entry is to include a plurality of delta values. A first delta value of the plurality of delta values represents a first distance between two cache lines associated with consecutive memory accesses within a second subregion of the memory region. The prefetch circuitry is further to detect a first memory access of a first cache line in the first subregion, identify prefetch candidates based on the first cache line and the plurality of delta values, and issue at least one prefetch request based on at least two of the prefetch candidates to be prefetched into a cache.

Region aware delta prefetcher

Various embodiments include methods and devices for portion interleaving for asymmetric size memory portions. Embodiments may include determining an asymmetric memory portion assignment for an interleave unit, determining a consumed address space offset for consumed address space of a memory, modifying an address of the interleave unit using the consumed address space offset, and assigning the interleave unit to an interleave granule in the asymmetric memory portion using the modified address in a compact manner before assigning another interleave unit to another interleave granule. Embodiments may include receiving an address of memory access request in a memory, mapping the address to an interleave granule in an asymmetric memory portion, assigning consecutive interleave units to the interleave granule while the interleave granule has unused space before assigning another interleave unit to another interleave granule, and implementing the memory access request at the mapped address.

Effective DRAM interleaving for asymmetric size channels or ranks while supporting improved partial array self-refresh

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Bengaluru, India

Swaraj Sha