Tata Consultancy Services Limited

Tata Consultancy Services Lmited

Swapnil Shashikant Rodi

Sunil Anant Puranik

Mahesh Damodar Barve

Manoj Karunakara Nambiar

Manoj Karunakaran Nambiar

Dhaval Shah

Barve Mahesh Damodar

Manesh Barve

High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen. This enables traceability of the code execution on the screen and printf/scanf statements output can be observed without any challenges.

Synthesizing printf and scanf statements for generating debug messages in high-level synthesis (HLS) code

Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.

Multiple field programmable gate array (FPGA) based multi-legged order transaction processing system and method thereof

Data processing and storage is an important part of a number of applications. Conventional data processing and storage systems utilize either a full array structure or a full linked list structure for storing data wherein the array consumes large amount of memory and linked list provides slow processing. Thus, conventional systems and methods are not capable of providing simultaneous optimization of memory consumption and time efficiency. The present disclosure provides an efficient way of storing data by creating an integrated array and linked list based structure. The data is stored in the integrated array and linked list based structure by using a delta based mechanism. The delta based mechanism helps in determining the location in the integrated array and linked list based structure where the data should be stored. The present disclosure incorporates the advantages of both array and linked list structure resulting in reduced memory consumption and latency.

Systems and methods for storing data in an integrated array and linked list based structure

The disclosure herein describes a method and a system for message based communication and failure recovery for FPGA middleware framework. A combination of FPGA and middleware framework provides a high throughput, low latency messaging and can reduce development time as most of the components can be re-used. Further the message based communication architecture built on a FPGA framework performs middleware activities that would enable reliable communication using TCP/UDP between different platforms regardless of their deployment. The proposed FPGA middleware framework provides for reliable communication of UDP based on TCP as well as failure recovery with minimum latency during a failover of an active FPGA framework during its operation, by using a passive FPGA in real-time and dynamic synchronization with the active FPGA.

Method and system for message based communication and failure recovery for FPGA middleware framework

This disclosure relates generally to methods and systems for providing exactly-once transaction semantics for fault tolerant FPGA based transaction systems. The systems comprise middleware components in a server as well as client end. The server comprises Hosts and FPGAs. The FPGAs control transaction execution (the application processing logic also resides in the FPGA) and provide fault tolerance with high performance by means of a modified TCP implementation. The Hosts buffer and persist transaction records for failure recovery and achieving exactly-once transaction semantics. The monitoring and fault detecting components are distributed across the FPGA's and Hosts. Exactly-once transaction semantics is implemented without sacrificing performance by switching between a high performance mode and a conservative mode depending on component failures. PCIE switches for connectivity between FPGAs and Hosts ensure FPGAs are available even if Hosts fail. When FPGA's provide higher processing elements and memory, the Hosts may be eliminated.

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Thane West, India

Swapnil Shashikant Rodi