Cadence Design Systems, Inc.

Swapnajit Chakraborti

Sandeep Pagey

Yael Duek-Golan

Boris Gommershtadt

Alok Jain

Erich Marschner

In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.

Systems for total coverage analysis and ranking of circuit designs

Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs

A mechanism is disclosed for recognizing and functionally abstracting a column of memory cells. According to one embodiment, a column of n (where n is an integer greater than 1) memory cells is identified in a description of a circuit. One of the n memory cells is selected as a representative memory cell. Then, the column of n memory cells is represented as a single-memory-cell column comprising the representative memory cell. The column is thereafter functionally abstracted to derive a logic-level representation of the memory cell. After that is done, n&#x2212;1 additional instances of the logic-level representation are generated. In this manner, the column of n memory cells is functionally abstracted as a column of n logic-level representations of the representative memory cell.

Mechanism for recognizing and abstracting memory structures

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Noida, India

Swapnajit Chakraborti