Globalfoundries Inc.

Swamy Muddu

Luigi Capodieci

Vito Dai

Sriram Madhavan

Shobhit Malik

Piyush Pathak

Rani Ghaida

Shangliang Jiang

Abde Ali Kagalwalla

Rani Abou Ghaida

Ahmed Mohyeldin

Via redundancy insertion is described. A via layout is analyzed by identifying each via, and for each via, identifying a location therefore in the layout, whether the via is redundant and a layout configuration for the via. Each via is classified into a bin of similar layout configurations. For each bin of redundant vias, possible via replacement candidates are determined from a database of possible replacement vias, and the candidates are ranked according to rule-based, recommendation-based and/or model-based criteria. For each via in each bin having a replacement(s), an optimal replacement is identified from among the ranked candidates taken in ranked order that first satisfies another criteria, such as not violating an applicable design rule. The layout is then updated with the optimal replacement.

Pattern-based via redundancy insertion

A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Layout pattern correction for integrated circuits

Methodologies and an apparatus enabling an improvement of a manufacturing yield of an IC design are disclosed. Embodiments include: determining a portion of a layout of an IC design, the portion including a first pattern including a plurality of design connections; determining a function performed by the first pattern based, at least in part, on the design connections; and selecting, by a processor, a second pattern based on the function.

Selection of replacement patterns for reducing manufacturing hotspots and constraint violations of IC designs

An approach is provided for applying post graphic data system (GDS) stream enhancements back to the design stage. Embodiments include receiving a data stream of an integrated circuit design layout from a design stage, determining one or more design constructs based on an analysis of the data stream, determining one or more instructions to implement the one or more design constructs at the design stage, and sending the instructions to the design stage to implement the one or more design constructs.

Method and apparatus for applying post graphic data system stream enhancements

Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.

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Milpitas, CA, United States of America

Swamy Muddu