Nvidia Corporation

Svetoslav D Tzvetkov

John Erik Lindholm

Brett Coon

Douglas A Voorhies

John R Nickolls

Simon S Moy

Bryon S Nordquist

Jerome Francis Duluk, Jr

Emmett Michael Kilgariff

Ming Yiu Siu

Andrew J Tao

Roger L Allen

Gary M Tarolli

Yan Yan Tang

Edward Colton Greene

Elena Ing

An occlusion prediction graphics processing system and method are presented in accordance with embodiments of the present invention. An occlusion prediction graphics processing method is utilized to predict which pixel values are eventually occluded before intermediate processing stages are performed on the pixel values. For example, occlusion results are predicted before the occlusion stage of a graphics pipeline. The occlusion prediction results are based upon an occlusion value received from later in a graphics processing pipeline (e.g., a raster operation stage). A convex polygonal prediction area can be established and a nearest vertex of the convex polygonal prediction area is selected for prediction analysis. Pixel values are removed or discarded from the pipeline based upon the occlusion prediction results and do not unnecessarily occupy processing resources. Removal of the pixel values from the pipeline includes pixels values associated with pixels in the convex polygonal prediction area. Pixel shading is performed on the remaining pixels.

Occlusion prediction graphics processing system and method

An occlusion prediction compressing system and method are presented in accordance with embodiments of the present invention. In one embodiment, an occlusion prediction graphics processing method is utilized to predict which pixels are eventually occluded before intermediate processing stages are performed on the pixels. Culling information utilized to predict which pixel are occluded is compressed in accordance with embodiments of the present invention. In one embodiment, a cull value for a pixel culling area is retrieved and an end of pipe depth value associated with a prediction area within the pixel culling area is received. A determination is made if the end of pipe depth value is within a threshold range of the cull value. The cull value is updated based upon the relationship of the end of pipe depth value to offsets from the cull value. The cull value is associated with a mask which indicates if a plurality of prediction areas are at or in front of the cull value.

Occlusion prediction compression system and method

A system, method and computer program product are provided for packing graphics attributes. In use, a plurality of graphics attributes is identified. Such graphics attributes are packed, such that the packed graphics attributes are capable of being processed utilizing a pixel shader.

System and method for graphics attribute packing for pixel shader usage

Resources to be used by concurrent threads in a multithreaded processor are allocated based on thread types of the threads. For each of at least two thread types, an amount of the resource is reserved, and amounts currently allocated are tracked. When a request to allocate some of the resource to a new thread is received, a determination as to whether the allocation can be made is based on the thread type of the new thread, the amount of the resource reserved for that thread type, and the amount currently allocated to threads of that type.

Thread-type-based resource allocation in a multithreaded processor

Resources to be used by concurrent threads in a multithreaded processor are allocated based on thread types of the threads, and thread-type-based criteria governing resource allocation decisions are dynamically modified based on feedback information indicating the degree to which various thread types are using the resource. For each of at least two thread types, an amount of the resource is reserved, and amounts currently allocated are tracked. When an allocation request for a new thread is received, the allocation is made or not based on the new thread's type, the amount of the resource reserved for that type, and the amount currently allocated to threads of that type. If, based on feedback information from the allocation decision, the amount of the resource reserved for one thread type is determined to be insufficient, the reserved amounts are modified to better meet the demand.

Thread-type-based load balancing in a multithreaded processor

One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. A disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture. Additional control instructions are used to set up thread processing target addresses for synchronization, breaks, and returns.

Structured programming control flow in a SIMD architecture

Circuits, methods, and apparatus that provide the die area and power savings of a single-ported memory with the performance advantages of a multiported memory. One example provides register allocation methods for storing data in a multiple-bank register file. In a thin register allocation method, data for a process is stored in a single bank. In this way, different processes use different banks to avoid conflicts. In a fat register allocation method, processes store data in each bank. In this way, if one process uses a large number of registers, those registers are spread among the banks, avoiding a situation where one bank is filled and other processes are forced to share a reduced number of banks. In a hybrid register allocation method, processes store data in more than one bank, but fewer than all the banks. Each of these methods may be combined in varying ways.

Register file allocation

One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determining if one or more threads diverge during execution of a conditional control instruction. Threads that exit a program are identified as idle by a disable mask. Other threads that are disabled may be enabled once the divergent threads reach an instruction that enables the disabled threads. Use of the disable mask allows for the use of conditional return and break instructions in a multithreaded SIMD architecture.

Structured programming control flow using a disable mask in a SIMD architecture

Early stencil rejection is used to improve throughput of a graphics processing pipeline. Early stencil rejection of some fragments may be performed prior to fragment shading using stencil test results based on a predicted stencil function. Early stencil rejection is performed when either the predicted stencil function matches the actual stencil function or the actual stencil function is a subset of the predicted stencil function. Early stencil rejection is performed without additional read accesses of a stencil buffer.

Early stencil test rejection

A system and method are provided for accelerating graphics processing utilizing multiple-pass rendering. Initially, geometry operations are performed on graphics data, and the graphics data is stored in memory. During a first rendering pass, various operations take place. For example, the graphics data is read from the memory, and the graphics data is rasterized. Moreover, first z-culling operations are performed utilizing the graphics data. Such first z-culling operations maintain a first occlusion image. During a second rendering pass, the graphics data is read from memory. Still yet, the graphics data is rasterized and second z-culling operations are performed utilizing the graphics data and the first occlusion image. Moreover, visibility operations are performed utilizing the graphics data and a second occlusion image. Raster-processor operations are also performed utilizing the graphics data, during the second rendering pass.

Growing community of inventors

Irvine, CA, United States of America

Svetoslav D Tzvetkov