Interuniversitair Microelektronica Centrum (imec)

Imec Vzw

Sven Wuytack

Francky Catthoor

Hugo De Man

Jean-Philippe Diguet

A formalized method for part of the design decisions, related to memory, involved while designing an essentially digital device is presented. The method shows how to traverse through and how to limit the search space being examined while solving these memory related design decisions. The method focuses on power consumption of said essentially digital device. A method for determining an optimized memory organization of an essentially digital device, wherein data reuse possibilities are explored, is described.

Method for determining an optimized memory organization of a digital device

A system and method for determining optimized scheduling intervals and optimized access conflicts and for determining an optimized memory organization of an essentially digital device. The system includes an optimizer for determining an optimized scheduling of the data access instructions for a plurality of disjunct code blocks, wherein each of the code blocks include part of the data access instructions. The system performs an iterative process of successively reducing the cycle budget for selected blocks and modifying the scheduling of the selected blocks until a cumulative cycle budget for all of the blocks is met.

A formalized method and a design system are described for part of the design decisions, related to memory, involved while designing an essentially digital device. The method and system determine an optimized memory organization starting from a representation of said digital device, the representation describing the functionality of the digital device and comprising data access instructions on basic groups, which are groups of scalar signals. The method and system determine optimized scheduling intervals of said data access instructions such that execution of said functionality with the digital device is guaranteed to be within a predetermined cycle budget, the determining of the optimized scheduling intervals comprising optimizing access conflicts with respect to an evaluation criterion related to the memory cost of said digital device. An optimized memory organization is selected in accordance with the optimized scheduling intervals and the optimized access conflicts.

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Sven Wuytack