Infineon Technologies Ag

Infineon Technologies Austria Ag

Qimonda Ag

Infineon Technologies Dresden Gmbh

International Business Machines Corporation

Globalfoundries Inc.

Nan Ya Technology Corporation

Infineon Technologies North America Corp.

Sven Schmidbauer

Alexander Ruf

Norbert Urbansky

Matthias Goldbach

Dirk Meinhold

Ravi Keshav Joshi

Michael Nelhiebel

Rainer Pelzer

Oliver Schilling

Paul Frank

Jens Hahn

Frank Wagner

Markus Fischer

Axel Buerke

Thomas Heinelt

Mark Hoinkis

Erhard Landgraf

Yi-Jen Lo

Roy Charles Iggulden

Peter Weigand

Tobias Mono

Michael Stadtmueller

Larry Clevenger

Robert Binder

Elke Erben

Dina Triyoso

Florian Schnabel

Stefan Weber

Stefan J Weber

Moritz Haupt

Hao Zhang

Chiang-Hung Lin

Oliver Gehring

Dietmar Henke

Wilhelm Claussen

Thomas Gärtner

Axel B&uuml;rke

Axel Bürke

A semiconductor device includes a semiconductor wafer or a single semiconductor chip or die, and a layer stack. The layer stack comprises a first layer comprising NiSi, and a second layer comprising NiV, wherein the second layer is arranged between the first layer and the semiconductor wafer or single semiconductor chip or die.

Semiconductor device having a layer stack, semiconductor arrangement and method for producing the same

Semiconductor device, semiconductor arrangement and method for producing the same

A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.

Method of manufacturing a semiconductor device having a power metallization structure

Power metallization structure for semiconductor devices

According to various embodiments, an electrode may include at least one layer including a chemical compound including aluminum and titanium.

Electrode, an electronic device, and a method for manufacturing an optoelectronic device

Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode.

Methods for fabricating integrated circuits with narrow, metal filled openings

An integrated circuit comprises a doped semiconductor portion including an amorphous portion and a contact structure comprising a conductive material. The contact structure is in contact with the amorphous portion. According to another embodiment, an integrated circuit comprises a doped semiconductor portion including a region having a non-stoichiometric composition and a contact structure comprising a conductive material. The contact structure is in contact with the region having a non-stoichiometric composition.

Integrated circuit comprising an amorphous region and method of manufacturing an integrated circuit

The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Method for manufacturing an integrated circuit including a transistor

A method for controlling a thickness of a first layer of an electrical contact of a semiconductor device, whereby the semiconductor device comprises a semiconductor layer, a first layer and a second layer, whereby at least a part of the semi-conductor layer is covered with the first layer, whereby at least a part of the first layer is covered with the second layer, whereby the second layer is exposed to a plasma gas, whereby an upper face of the first layer adjacent to the second layer is treated by the plasma gas and an interlayer is generated between the first and the second layer reducing the thickness of the first layer.

Method for controlling a thickness of a first layer and method for adjusting the thickness of different first layers

A process for producing aluminum-filled contact holes in a wafer is disclosed. The process uses a coating installation that includes a plurality of vacuum-processing chambers that are coupled to one another via at least one transfer chamber with an associated handler for transferring the wafers. The preferred process including forming the contact holes and depositing a barrier layer. The wafer is cooled to ambient temperature. A cold aluminum PVD coating process can then be carried out in a PVD-aluminum ESC chamber. After the wafer is heated (e.g., to a temperature of less than about 450&#xb0; C.), a hot aluminum PVD deposition process is carried out in the PVD-aluminum ESC chamber.

Process for producing aluminum-filled contact holes

A method makes contact with a doping region formed at a substrate surface of a substrate. An insulating layer is applied on the substrate surface and a contact hole is formed in the insulating layer. A metal-containing layer is subsequently deposited on the insulating layer and the surface region of the doping region that is uncovered by the contact hole. In a subsequent thermal process having two steps, first the metal-containing layer is reacted with the silicon of the doping region to form a metal silicide layer and then the rest of the metal-containing layer is converted into a metal-nitride-containing layer in a second thermal step.

Method for making contact with a doping region of a semiconductor component

A process for fabricating an interconnect for contact holes includes forming contact holes in an insulation layer leading to a first interconnect layer, cleaning the hole surface, forming a barrier layer on the hole surface, forming an AlGeCu-containing second interconnect layer on the insulation surface by a low-temperature PVD process to fill up the contact holes, forming and patterning a mask layer, and patterning the second interconnect layer by an anisotropic etching process using the mask layer. Due to the relatively small grain sizes and precipitations that are formed in the process, the layer can be patterned directly in a subsequent patterning step, resulting in an extremely reliable and inexpensive interconnect that is easy to integrate in existing process sequences.

Process for fabricating an interconnect for contact holes

A method for depositing a two-layer diffusion barrier on a semiconductor wafer consisting of a TaN layer and a Ta layer serving as a carrier layer for copper interconnects. The TaN layer is inventively deposited at temperatures above 200&deg; C. in a first step, and the Ta layer is deposited in a second step while cooling the semiconductor wafer to a temperature below 50&deg; C.

Method for depositing a two-layer diffusion barrier

A process for producing metal-containing layers, in particular metal-containing diffusion barriers, contact layers and/or antireflection layers. The process according to the invention has a first step in which a metal layer having a predetermined thickness at an elevated temperature is applied to a semiconductor structure. Next, the metal layer is cooled in a nitrogen-containing atmosphere, resulting in a metal nitride layer being formed.

Process for producing metal-containing layers

Growing community of inventors

Dresden, Germany

Sven Schmidbauer