Globalfoundries Inc.

Advanced Micro Devices Corporation

Globalfoundries U.S. Inc.

Globalfoundries Dresden Module One Limited Liability Company & Kg

Sven Beyer

Jan Hoentschel

Thilo Scheiper

Uwe Griebenow

Ralf Richter

Richard Carter

Martin Trentzsch

Alexander Ebermann

Andy C Wei

Manfred Horstmann

Klaus Hempel

Patrick Press

Elliot John Smith

Berthold Reimer

Robert Binder

Peter Javorka

Markus Lenski

Rohit Pal

Rolf Stephan

Nigel Chan

Carsten Grass

Wolfgang Buchholtz

Falk Graetsch

Karla Romero

Stefan Dünkel

Peter Baars

Frank Wirbeleit

Christoph Schwan

Gunter Grasshoff

Tom Herrmann

Stephan Kruegel

Frank Seliger

Markus Forsberg

Halid Mulaosmanovic

Joachim Metzger

Joe Bloomquist

Stefan Duenkel

Andreas Hellmich

Steffen Laufer

Tom Hasche

Jan Paul

Stefanie Steiner

Stefan Flachowsky

Kai Frohberg

Thorsten E Kammler

Venkatesh P Gopinath

Navneet Jain

Thomas Feudel

Hans-Juergen Thees

Alban Zaka

Andreas Kurz

El Mehdi Bazizi

Christopher Michael Prindle

Martin Mazur

Katrin Reiche

Andreas Ott

Kerstin Ruttloff

Johannes Von Kluge

Zhi-Yuan Wu

Rick J Carter

Dominik M Kleimaier

Boris Bayha

Erik P Geiss

Rainer Giedigkeit

Roland Stejskal

Johannes Müller

Kamatchi Subramanian

Martin Schulze

Jochen Willi Poth

Sandhya Chandrashekhar

Gerhard Lembach

Axel Henke

Klaus Gebauer

Thilo Sheiper

An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.

IC structure with MFMIS memory cell and CMOS transistor

Structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor. The structure comprises a gate stack having a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.

Structures for a ferroelectric field-effect transistor and related methods

The structure includes transistors in rows and columns and each having an electric field-based programmable threshold voltage at either a first threshold voltage (VT) or a second VT. The structure further includes first and second signal lines for the rows and columns, respectively. Each first signal line is connected to transistors in a row and each second signal line is connected to transistors in a column. When operated in a switch mode, the transistors may or may not become conductive depending upon their respective VTs. Conductive transistors form connected pairs of first and second signal lines and, thus, create signal paths. The structure can also include mode control circuitry to selectively operate the transistors in either a program mode to set a first VT or an erase mode to set a second VT and to concurrently operate the transistors in the switch mode.

Structure including a cross-bar router and method

In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

Transistor element including a buried insulating layer having enhanced functionality

A method includes forming a stack of semiconductor die. The stack includes a first semiconductor die, a second semiconductor die and a third semiconductor die. The first semiconductor die is stacked above the second semiconductor die and the third semiconductor die is stacked above the first semiconductor die. A first optical transmitter and a first optical receiver are provided in the first semiconductor die, a second optical transmitter is provided in the second semiconductor die, and a second optical receiver is provided in the third semiconductor die. A first optical signal is transmitted from the first optical transmitter in the first semiconductor die to the second optical receiver in the third semiconductor die. A second optical signal is transmitted from the second optical transmitter in the second semiconductor die to the first optical receiver in the first semiconductor die.

Communicating optical signals between stacked dies

An integrated circuit product includes a silicon-on-insulator (SOI) substrate and a flash memory device positioned in a first area of the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulating layer positioned above the semiconductor bulk substrate, and a semiconductor layer positioned above the buried insulating layer, and the flash memory device includes a flash transistor device and a read transistor device. The flash transistor device includes a floating gate, an insulating layer positioned above the floating gate, and a control gate positioned above the insulating layer, wherein the floating gate includes a portion of the semiconductor layer. The read transistor device includes a gate dielectric layer positioned above the semiconductor bulk substrate and a read gate electrode positioned above the gate dielectric layer.

Flash memory device

Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

Ferro-FET device with buried buffer/ferroelectric layer stack

A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

Methods for forming integrated circuits that include a dummy gate structure

The present disclosure provides in one aspect a semiconductor device including a substrate structure comprising an active semiconductor material formed over a base substrate and a buried insulating material formed between the active semiconductor material and the base substrate, a ferroelectric gate structure disposed over the active semiconductor material in an active region of the substrate structure, the ferroelectric gate structure comprising a gate electrode and a ferroelectric material layer, and a contact region formed in the base substrate under the ferroelectric gate structure.

NVM device in SOI technology and method of fabricating an according device

In illustrative embodiments disclosed herein, a logic element may be provided on the basis of a non-volatile storage mechanism, such as ferroelectric transistor elements, wherein the functional behavior may be adjusted or programmed on the basis of a shift of threshold voltages. To this end, a P-type transistor element and an N-type transistor element may be connected in parallel, while a ferroelectric material may be used so as to establish a first polarization state resulting in a first functional behavior and a second polarization state resulting in a second different functional behavior. For example, the logic element may enable a switching between P-type transistor behavior and N-type transistor behavior depending on the polarization state.

Programmable logic elements and methods of operating the same

A method of manufacturing a flash memory device is provided including providing a silicon-on-insulator (SOI) substrate, in particular, a fully depleted silicon-on-insulator (FDSOI) substrate, comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer and forming a memory device on the SOI substrate. Forming the flash memory device on the SOI substrate includes forming a flash transistor device and a read transistor device.

A semiconductor die is provided with an optical transmitter configured to transmit an optical signal to another die and an optical receiver configured to receive an optical signal from another die. Furthermore, a method of forming a semiconductor device is provided including forming a first semiconductor die with the steps of providing a semiconductor substrate, forming a transistor device at least partially over the semiconductor substrate, forming an optical receiver one of at least partially over and at least partially in the semiconductor substrate, forming a metallization layer over the transistor device, and forming an optical transmitter one of at least partially over the metallization layer and at least partially in the metallization layer.

Die-die stacking

An integrated circuit includes a first transistor, a second transistor and a dummy gate structure. The first transistor includes a first gate structure. The first gate structure includes a first gate insulation layer including a high-k dielectric material and a first gate electrode. The second transistor includes a second gate structure. The second gate structure includes a second gate insulation layer including the high-k dielectric material and a second gate electrode. The dummy gate structure is arranged between the first transistor and the second transistor and substantially does not include the high-k dielectric material.

Integrated circuit including a dummy gate structure and method for the formation thereof

A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.

Semiconductor device with a memory device and a high-K metal gate transistor

A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.

Semiconductor structure including a nonvolatile memory cell and method for the formation thereof

Growing community of inventors

Dresden, Germany

Sven Beyer