Intel Corporation

Infineon Technologies Ag

Intel Mobile Communications Gmbh

Intel Deutschland Gmbh

Intel IP Corporation

Intel IP Corportaion

Google Inc.

Sven Albers

Georg Seidemann

Christian Geissler

Andreas Wolter

Klaus Reingruber

Thorsten Meyer

Marc Dittes

Hans-Joachim Barth

Thomas Wagner

Richard Patten

Gerald Ofner

Sonja Koller

Michael P Skinner

Reinhard Mahnkopf

Teodora Ossiander

Harald Gossner

Bernd Waidhas

Wolfgang Molzer

Peter Baumgartner

Gernot Langguth

Klaus Diefenbeck

Edmund Goetz

Jan Proschwitz

Bernd Eisener

Bernd Memmler

Christian Mueller

Christian Lehrer

Karl-Heinz Malek

Eberhard Rohrer

Klaus Jürgen Reingruber

Carsten Ahrens

Markus Brunnbauer

Ulrich Krumbein

Sandeep B Sane

Gunther Mackh

Andreas Augustin

Philipp Riess

Stephan Stoeckl

Berthold Schuderer

Shubhada H Sahasrabudhe

Bastiaan Elshof

Frank Zudock

David O'Sullivan

Reinhard Golly

Klaus Gnannt

Alexandra Atzesdorfer

Bernd Ebersberger

Patrick Schelauske

Christian Müller

Christian Georg Geissler

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

Package stacking using chip to wafer bonding

An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.

Wafer level package structure with internal conductive layer

An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

Semiconductor die package with more than one hanging die

Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.

Integrated circuit packages including an optical redistribution layer

Disclosed herein are electronic components having three-dimensional capacitors disposed in a metallization stack, as well as related methods and devices. In some embodiments, for example, an electronic component may include: a metallization stack and a capacitor disposed in the metallization stack wherein the capacitor includes a first conductive plate having a plurality of recesses, and a second conductive plate having a plurality of projections, wherein individual projections of the plurality of projections extend into corresponding individual recesses of the plurality of recesses without contacting the first conductive plate.

Electronic components having three-dimensional capacitors in a metallization stack

Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

Semiconductor package having a variable redistribution layer thickness

An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.

Electrical device and a method for forming an electrical device

A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Microelectronic package having a passive microelectronic device disposed within a package body

A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.

Vertical wire connections for integrated circuit package

A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.

Microelectronic package with illuminated backside exterior

A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

System-in-package devices and methods for forming system-in-package devices

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Integrated circuit package configurations to reduce stiffness

A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

Flexible band wearable electronic device

Growing community of inventors

Wuppertal, Germany

Sven Albers