Advanced Micro Devices Corporation

Spansion Llc.

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Cypress Semiconductor Corporation

Spansion LLC Advanced Micro Devices, Inc

Suzette Keefe Pangrle

Minh Van Ngo

Steven C Avanzino

Nicholas H Tripsas

Matthew S Buynoski

Uzodinma Okoroanyanwu

Manuj Rathor

Fei Wang

Jeffrey Allan Shields

Ramkumar Subramanian

Sameer S Haddad

Lu You

Angela Tai Hui

Dawn M Hopper

An Chen

Connie Pin-Chin Wang

Michael A VanBuskirk

Paul Raymond Besser

Sergey D Lopatin

Calvin T Gabriel

Christy Mei-Chu Woo

Kashmir S Sahota

Lynne A Okada

Igor Sokolik

Zoran Krivokapic

Christopher F Lyons

Richard J Huang

Bryan K Choo

Richard Paul Kingsborough

Scott P McGrath

James J Xie

Michael Vanbuskirk

Christie Marrian

Jeffrey S Leal

Kevin Song

Susan Tovar

Mark T Ramsbey

Mark S Chang

Amit P Marathe

Pin-Chin Connie Wang

Reynaldo Co

Lewis N Shen

Alexander H Nickel

Wenge Yang

John Espinoza Sanchez, Jr

Kathleen R Early

Zhida Lan

John G Pellerin

Maria Chow Chan

Joffre F Bernard

Grant Villavicencio

Jane V Oglesby

William G Leonard

Keith L Barrie

Ernesto A Gallardo

Elmer M Del Rosario

John R Bray

Colin Stewart Bill

Simon S Chan

Shekhar Pramanick

Darrell M Erb

Minh Quoc Tran

Kai Yang

Robert A Huertas

Juri Krieger

Hieu T Pham

Swaroop Kaza

Tzu-Ning Fang

Dongxiang Liao

Stuart Spitzer

Ercan Adem

Patrick K Cheung

Jinsong Yin

Robert J Chiu

John Sanchez

David Gaun

Yi-Ching Jean Wu

Jeremias D Romero

Ashok M Khathuria

Wei Daisy Cai

DeAnn Eileen Melcher

Nicolay F Yudanov

Alline F Myers

Loreto Cantillep

Simon McElrea

De Ann Eileen Melcher

Robert Matthew Ulfig

Stephan Keetai Park

Jeffery A Shields

Ravi Shenoy

Ecran Adem

Ramkumar Subramanion

Chakku Gopalan

James Xie

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

Electrical connector between die pad and z-interconnect for stacked die assemblies

A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Damascene metal-insulator-metal (MIM) device with improved scaleability

Methods are disclosed for improving electrical interconnection in stacked die assemblies, and stacked die assemblies are disclosed having structural features formed by the methods. The resulting stacked die assemblies are characterized by having reduced electrical interconnect failure.

Stacked die assembly having reduced stress electrical interconnects

In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.

Diode and resistive memory device structures

The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

Metal-insulator-metal-insulator-metal (MIMIM) memory device

An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H. A glue layer may be provided between the gettering layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.

Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device

The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Damascene metal-insulator-metal (MIM) device

In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Test structures for development of metal-insulator-metal (MIM) devices

Disclosed are semiconductor memory devices containing a plastic substrate and at least one active device supported by the plastic substrate, the active device containing an organic semiconductor material. The semiconductor memory devices containing a plastic substrate may further contain a polymer dielectric and/or a conductive polymer.

Semiconductor device built on plastic substrate

Disclosed are organic semiconductor devices containing a copolymer layer that contains a polymer dielectric and a semiconducting polymer formed using actinic radiation. As initially formed, the copolymer layer has dielectric properties, but portions may selectively rendered conductive after those portions are exposed to actinic radiation. Also disclosed are methods of making the organic semiconductor devices. Such devices are characterized by light weight and robust reliability.

Processing a copolymer to form a polymer memory cell

The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers&#x2014;respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.

Stacked organic memory devices and methods of operating and fabricating

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Cupertino, CA, United States of America

Suzette Keefe Pangrle