Intel Corporation

Suzanne S Rich

Charles Henry Wallace

Leonard P Guler

Swaminathan Sivakumar

Richard E Schenker

Paul Anton Nyhus

Mohit K Haran

Curtis W Ward

Michael Harper

Reken Patel

Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a first interlayer dielectric (ILD), a plurality of source/drain (S/D) contacts in the first ILD, a plurality of gate contacts in the first ILD, wherein the gate contacts and the S/D contacts are arranged in an alternating pattern, and wherein top surfaces of the gate contacts are below top surfaces of the S/D contacts so that a channel defined by sidewall surfaces of the first ILD is positioned over each of the gate contacts, mask layer partially filling a first channel over a first gate contact, and a fill metal filling a second channel over a second gate contact that is adjacent to the first gate contact.

1D vertical edge blocking (VEB) via and plug

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Hillsboro, OR, United States of America

Suzanne S Rich