3com Corporation

Suzanne M Hughes

Tadhg Creedon

Vincent Gavin

Mike Lardner

Kevin Jennings

Denise De Paor

Kevin J Hyland

Derek Coburn

Brendan Walsh

Sean Boylan

Susan M Pratt

Padraic O'Reilly

A program tool automatically generating interconnect logic for a system-on-a-chip is based on a library of operational cores and on a architecture which requires all data exchange between cores to proceed via shared memory, which may be 'off-chip'. The architecture includes a data aggregation technique for access to memory with successive levels of arbitration.

Automatic generation of interconnect logic components

An architecture for a system on a chip wherein functional cores have wrappers for compatibility with a common bus system and the bus system includes aggregators for bus transactions of different speeds and/or bus widths.

Asic system architecture including data aggregation technique

A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.

Clocking scheme for ASIC

Growing community of inventors

Barna, Ireland

Suzanne M Hughes