Korea Institute of Science and Technology

Samsung Electronics Co., Ltd.

Suyoun Lee

Jong-Keuk Park

Joon Young Kwak

Jaewook Kim

InHo Kim

Yeonjoo Jeong

Jongkil Park

Kyeong Seok Lee

Won Mok Kim

Jeung-hyun Jeong

Taek Sung Lee

Byung-ki Cheong

Hyun Seok Lee

Gyuweon Hwang

Hansoo Kim

Sunil Shim

Jaehoon Jang

Jaehun Jeong

Seon Jeong Kim

Young Joon Baik

Jung-hyeon Kim

Gyu Weon Hwang

Byung Ki Cheong

Hyunsu Ju

Seongsik Park

Sudong Kim

Jooho Kim

Sang-Yeol Shin

Hyung-Woo Ahn

Wook Yeon Hwang

Eunpyo Park

Kyu Sik Mun

A neuromorphic circuit according to example embodiments of inventive concepts includes a first neuron array including a plurality of neuron circuits generating a spike signal; a first synapse array including a plurality of first synapse circuits to process and output the spike signal transmitted from the first neuron array; a second synapse array including a plurality of second synapse circuits; a first connecting block positioned between the first synapse array and the second synapse array and connecting the first synapse array and the second synapse array in response to a control signal; and a control logic to generate the control signal. The neuromorphic circuit may easily expand the size of the synapse element array to a desired size by using a connecting block.

Expandable neuromorphic circuit

The present disclosure relates to a nonlinearity compensation circuit for a memristive device. The circuit according to an embodiment includes at least one power source unit to apply an input pulse; a modulation unit connected to the at least one power source unit to adjust a pulse width of an update pulse to be applied to the memristive device; and the memristive device to which the modulated update pulse is applied.

Nonlinearity compensation circuit for memristive device

Embodiments of inventive concepts relate to a neuromorphic circuit including a flash memory-based spike regulator capable of generating a stable spike signal with a small number of devices. The neuromorphic circuit may generate a simple and stable spike signal using a flash memory-based spike regulator. Therefore, it is possible to implement a semiconductor neuromorphic circuit at low power and low cost by using the spike regulator of the present invention. Example embodiments of inventive concepts provide a neuromorphic circuit comprising a control signal generator for generating a control signal for generating a pulse signal; and a spike regulator for generating a spike signal in response to the control signal. Wherein the spike regulator comprises a first transistor for switching an input signal transmitted to one terminal to the other terminal in response to the control signal; and a first flash memory type transistor having a drain terminal connected to the other terminal of the first transistor and transferring the switched input signal to a source terminal as a spike signal.

Neuromorphic circuit including spike regulator based on flash memory

A flash memory device is provided. The flash memory device is disposed on a substrate, a channel layer made of a two-dimensional material, sources and drains disposed at both ends of the channel layer, a tunneling insulating layer having a first dielectric constant and a tunneling insulating layer disposed on the channel layer, a floating gate made of a two-dimensional material, a blocking insulating layer disposed on the floating gate and having a second dielectric constant greater than the first dielectric constant, and an upper gate disposed on the blocking insulating layer.

Flash memory device used in neuromorphic computing system

An artificial neuron device according to an embodiment of the present disclosure includes a first resistor connected between an input terminal and a first node; a capacitor connected between the first node and a ground terminal; a threshold switch connected between the first node and a second node; and a second resistor connected between the second node and the ground terminal, wherein, when an input voltage of a certain level is applied to the input terminal by time, a membrane potential occurs at the first node and a spike current flows through the second node. According to present disclosure, the artificial neuron device expresses the Integrate-and-Fire function, the rate coding ability, the SFA characteristics, and the chaotic activity of the biological neuron, and therefore may be widely used for the artificial neuron network device, the large-scale brain-inspired computing system, and the artificial intelligence (AI) system.

Artificial neuron device using ovonic threshold switch, artificial neuron chip and user apparatus including the same

A nano-oscillator device includes a switching element configured to be switched to an ON state at a threshold voltage or above and switched to an OFF state below a holding voltage; and a load element connected to the switching element in series. In the nano-oscillator device, vibration characteristics are implemented by using a switching element and a load element connected thereto in series. Also, the oscillation frequency of the output waveform of the oscillator may be adjusted in real time according to a gate voltage by using a field effect transistor serving as a load element. Using a synchronization characteristic in which the oscillation frequency and phase are locked with respect to an external input, it is possible to implement a computing system based on a network in which a plurality of oscillator devices are coupled.

Frequency-tunable nano-oscillator device and computing unit using the same

Disclosed is a method for manufacturing a chalcogenide switching device, which includes forming a first electrode on a substrate, forming a chalcogenide material composed of Geand Seformed on the first electrode, and forming a second electrode on the chalcogenide material, wherein the value x is greater than 0 and smaller than 1. A chalcogenide switching device manufactured by this method is also disclosed.

Chalcogenide switching device using germanium and selenium and manufacturing method thereof

A vertical NAND string nonvolatile memory device can include an upper dopant region disposed at an upper portion of an active pattern and can have a lower surface located a level higher than an upper surface of an upper selection gate pattern. A lower dopant region can be disposed at a lower portion of the active pattern and can have an upper surface located at a level lower than a lower surface of a lower selection gate pattern.

Nonvolatile memory device

Disclosed is a method for growing a thin film, which includes modifying a surface grain size and surface roughness on a thin film to improve the mobility of a carrier and a light scattering effect. The method for growing a thin film includes: forming nuclei of grains having various grain orientations on a substrate; causing first grains having a first specific grain orientation to grow predominantly among the grains having various grain orientations, thereby forming a first preferred texture comprised of the predominantly grown first grains; and then causing second grains having a second grain orientation to grow predominantly, thereby forming a second preferred texture comprised of the predominantly grown second grains, wherein the surface grain size of each of the second grains forming the second texture is larger than that of each of the first grains forming the first texture.

Method for growing thin film

A super-resolution optical recording medium includes a reflective layer formed on a substrate, a recording layer for recording information thereon, a super-resolution layer made of a chalcogenide semiconductor material, and a first and a second dielectric layers laminated on upper and lower surfaces of the super-resolution layer. The recording layer is made of a material that has a decomposition temperature higher than an information reproduction temperature and does not form bubble recording marks during recording, and the super-resolution layer contains one or more elements selected from the group consisting of nitrogen, oxygen, carbon, and boron.

Optical recording medium having super-resolution structure for improvement of reproducing stability and noise characteristic in low frequency band

A super-resolution material for recording and reproducing optical information, comprises a semiconductor material which has a transmittance that increases with an increasing intensity of the incident radiation, and one or more elements selected from the group consisting of nitrogen (N), oxygen (O), carbon (C) and boron (B).

Super-resolution material and high density optical information storage medium using same

A phase change memory apparatus includes a phase change memory array in which a plurality of phase change memory devices are arranged, and a pulse generator that supplies a writing current pulse, an erasure current pulse, and a reverse repair current pulse to the phase change memory devices in the phase change memory array. The reverse repair current pulse has opposite direction to the writing current pulse and the erasure current pulse of the phase change memory devices, and is of such a size that resultant Joule heat and electromigration move the elements of the reverse repair current pulse. The reverse repair current pulse has a width equal to or more than a smaller one of duration of a normal writing operation and duration of a normal erasure operation.

Growing community of inventors

Yongin-si, South Korea

Suyoun Lee