Samsung Electronics Co., Ltd.

Suyeon Doo

Taeyoung Oh

Chulsung Park

Namjong Kim

Young-Sik Kim

Young-Ju Kim

Seungjun Bae

Yoon-Joo Eom

Yongjae Lee

Hye Jung Kwon

A memory device includes memory cell array including a plurality of memory cells that store data, a first transmitter that transmits the data to an external device through a first data line, and a ZQ controller that performs a ZQ calibration operation to generate a first ZQ code for impedance matching of the first data line. The first transmitter encodes the first ZQ code and the first data based on a first clock and drives the first data line based on the encoded result based on a second clock.

Memory device and operation method thereof

A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is configured to determine a number of times to perform a target row refresh (TRR) in response to a mode register set (MRS) code signal, wherein the MRS code signal is generated in response to a temperature change, and the refresh control circuit is configured to maintain a refresh cycle of at least two of the memory cells for a period of time when the refresh cycle is changed due to the temperature change.

Semiconductor memory device that includes a refresh control circuit that maintains a refresh cycle when an MRS code signal is changed due to temperature

Semiconductor memory device that performs a refresh operation

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Seoul, South Korea

Suyeon Doo