Qualcomm Incorporated

Suvam Chatterjee

Kalyan Kumar Bhiravabhatla

Vishwanath Shashikant Nikam

Abhishek Lal

Andrew Evan Gruber

Ankit Kumar Singh

Sampathkumar Periasamy

Siva Satyanarayana Kola

Renju Boben

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for variable rate tessellation. A graphics processor may receive data for geometry processing of a plurality of patches in a draw call. The graphics processor may reduce a tessellation factor of each of the plurality of patches based on a property of each of the plurality of patches. The reduced tessellation factor may correspond to a TRF. The property may correspond to a shading rate or a number of visible pixels. The graphics processor may apply the TRF for each of the plurality of patches. The graphics processor may render each of the plurality of patches based on the applied TRF for each of the plurality of patches.

Variable rate tessellation

The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of indices for each of a plurality of primitives. The apparatus may also determine a size of each of a plurality of primitive batches, each of the plurality of primitive batches including at least one primitive of the plurality of primitives. Additionally, the apparatus may divide, based on the determined size of each of the plurality of primitive batches, the plurality of primitives into the plurality of primitive batches. The apparatus may also distribute each of the plurality of primitive batches to each of a plurality of geometry slices, each of the plurality of geometry slices including one or more primitives of the plurality of primitives.

Methods and apparatus for scalable primitive rate architecture for geometry processing

Growing community of inventors

Bengaluru, India

Suvam Chatterjee