Cadence Design Systems, Inc.

Sutirtha Kabir

Arnold Jean Marie Gustave Ginetti

Balvinder Singh

Steve Song Lee

Madhur Sharma

Reenee Raizada Tayal

Xavier Alasseur

Vishal Agarwal

Diwakar Mohan

Jean-Noel Francois Philippe Marie Pic

Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.

Methods, systems, and computer program product for characterizing an electronic design with a schematic driven extracted view

Disclosed are methods, systems, and articles of manufacture for characterizing electronic designs with electronic design simplification techniques. These techniques identify an input for simplifying an electronic design and generates a simplified electronic design at least by performing layout simplification on the electronic design. A characterization input may be determined for subsequent characterization of the simplified electronic design. An electromagnetic behavior of the simplified electronic design may then be characterized using at least the characterization input.

Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques

A computer may generate a record of a template associated with a schematic design corresponding to an integrated circuit design. The template may have one or more instances corresponding to one or more initial parameters associated with a chain of one or more transmission line components of the integrated circuit design. The computer may then modify content of the chain of one or more transmission line components in a circuit layout corresponding to the schematic design within the maximum range limit of the one or more initial parameters. The computer may update the one or more instances according to modified contents of the one or more transmission line components in the circuit layout.

Methods for layout driven synthesis of transmission line routes in integrated circuits

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Chandler, AZ, United States of America

Sutirtha Kabir